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TMS320VC5407PGE 参数 Datasheet PDF下载

TMS320VC5407PGE图片预览
型号: TMS320VC5407PGE
PDF下载: 下载PDF文件 查看货源
内容描述: 定点数字信号处理器 [Fixed-Point Digital Signal Processors]
分类和应用: 数字信号处理器
文件页数/大小: 110 页 / 1351 K
品牌: TI [ TEXAS INSTRUMENTS ]
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Electrical Specifications  
Table 527. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)  
MASTER  
SLAVE  
UNIT  
MIN  
12  
4
MAX  
MIN  
MAX  
t
t
Setup time, BDR valid before BCLKX low  
Hold time, BDR valid after BCLKX high  
2 6P  
ns  
ns  
su(BDRV-BCKXL)  
5 + 12P  
h(BCKXH-BDRV)  
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.  
P = 0.5 * processor clock  
Table 528. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)  
§
MASTER  
SLAVE  
PARAMETER  
UNIT  
MIN  
MAX  
MIN  
MAX  
t
t
t
Hold time, BFSX low after BCLKX low  
C 3 C + 4  
T 4 T + 3  
ns  
ns  
ns  
h(BCKXL-BFXL)  
d(BFXL-BCKXH)  
d(BCKXL-BDXV)  
#
Delay time, BFSX low to BCLKX high  
Delay time, BCLKX low to BDX valid  
4  
5
6P + 2  
10P + 17  
Disable time, BDX high impedance following last data bit from  
BCLKX low  
t
2  
4
6P 4  
10P + 17  
ns  
ns  
dis(BCKXL-BDXHZ)  
t
Delay time, BFSX low to BDX valid  
D 2 D + 4 4P + 2  
8P + 17  
d(BFXL-BDXV)  
§
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.  
P = 0.5 * processor clock  
T
=
=
=
BCLKX period = (1 + CLKGDV) * 2P  
C
D
BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even  
BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2P when CLKGDV is even  
#
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX  
and BFSR is inverted before being used internally.  
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP  
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP  
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock  
(BCLKX).  
MSB  
LSB  
BCLKX  
t
t
d(BFXL-BCKXH)  
h(BCKXL-BFXL)  
BFSX  
t
t
t
d(BCKXL-BDXV)  
d(BFXL-BDXV)  
dis(BCKXL-BDXHZ)  
BDX  
Bit 0  
Bit(n-1)  
Bit(n-1)  
(n-2)  
(n-3)  
(n-4)  
t
su(BDRV-BCKXL)  
t
h(BCKXH-BDRV)  
BDR  
Bit 0  
(n-2)  
(n-3)  
(n-4)  
Figure 525. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0  
97  
November 2001 Revised April 2004  
SPRS007D  
 
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