Electrical Specifications
Table 5−36. HPI16 Mode Switching Characteristics
PARAMETER
t
d(DSL-HDD)
Delay time, DS low to HD driven
Case 1a: Memory accesses initiated immediately following a write
when DMAC is active in 16-bit mode and t
w(DSH)
was < 18H
Case 1b: Memory accesses not immediately following a write when
DMAC is active in 16-bit mode
Delay time,
DS low to HD
valid for first
word of an
HPI read
Case 1c: Memory accesses initiated immediately following a write
when DMAC is active in 32-bit mode and t
w(DSH)
was < 26H
Case 1d: Memory access not immediately following a write when
DMAC is active in 32-bit mode
Case 2a: Memory accesses initiated immediately following a write
when DMAC is inactive and t
w(DSH)
was < 10H
Case 2b: Memory accesses not immediately following a write when
DMAC is inactive
t
d(DSH-HYH)
d(DSH HYH)
t
v(HYH-HDV)
t
h(DSH-HDV)R
t
d(COH-HYH)
t
d(DSL-HYL)
t
d(DSH−HYL)
Delay
time
time,
DS high to
HRDY high
Memory writes when no DMA is active
Memory writes with one or more 16-bit DMA channels active
Memory writes with one or more 32-bit DMA channels active
1
MIN
0
MAX
10
32P + 20
−
t
w(DSH)
16P + 20
48P + 20
−
t
w(DSH)
ns
24P + 20
20P + 20
−
t
w(DSH)
10P + 20
10P + 5
16P + 5
24P + 5
7
6
5
12
12
ns
ns
ns
ns
ns
ns
UNIT
ns
t
d(DSL-HDV1)
Valid time, HD valid after HRDY high
Hold time, HD valid after DS rising edge, read
Delay time, CLKOUT rising edge to HRDY high
Delay time, DS low to HRDY low
Delay time, DS high to HRDY low
HCS
t
w(DSH)
t
c(DSH−DSH)
HDS
t
su(HBV−DSL)
t
su(HBV−DSL)
t
w(DSL)
t
h(DSL−HBV)
t
h(DSL−HBV)
HR/W
t
su(HAV−DSL)
HA[17:0]
Valid Address
t
h(DSH−HDV)R
t
d(DSL−HDV1)
HD[15:0]
t
d(DSL−HDD)
t
v(HYH−HDV)
HRDY
t
d(DSL−HYL)
Data
t
d(DSL−HDD)
t
h(DSH−HAV)
Valid Address
t
d(DSL−HDV1)
Data
t
v(HYH−HDV)
t
h(DSH−HDV)R
t
d(DSL−HYL)
Figure 5−32. Nonmultiplexed Read Timings
November 2001
−
Revised April 2004
SPRS007D
105
TI [ TEXAS INSTRUMENTS ]
