Electrical Specifications
†
Table 5−22. McBSP Transmit and Receive Switching Characteristics
PARAMETER
MIN
MAX
UNIT
ns
‡
t
t
t
Cycle time, BCLKR/X
BCLKR/X int
BCLKR/X int
4P
c(BCKRX)
§
§
Pulse duration, BCLKR/X high
Pulse duration, BCLKR/X low
D − 1
D + 1
ns
w(BCKRXH)
w(BCKRXL)
§
§
BCLKR/X int
BCLKR int
BCLKR ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BFSX int
C − 1
C + 1
ns
ns
ns
− 3
0
3
12
5
t
t
t
t
t
Delay time, BCLKR high to internal BFSR valid
Delay time, BCLKX high to internal BFSX valid
d(BCKRH-BFRV)
d(BCKXH-BFXV)
dis(BCKXH-BDXHZ)
d(BCKXH-BDXV)
d(BFXH-BDXV)
− 1
2
ns
ns
ns
ns
10
6
Disable time, BCLKX high to BDX high impedance following last data
bit of transfer
10
10
20
7
¶
− 1
#
Delay time, BCLKX high to BDX valid
Delay time, BFSX high to BDX valid
DXENA = 0
2
¶
−1
ONLY applies when in data delay 0 (XDATDLY = 00b) mode
BFSX ext
2
11
†
‡
§
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
P = 0.5 * processor clock
T
C
D
=
=
=
BCLKRX period = (1 + CLKGDV) * 2P
BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2P when CLKGDV is even
¶
#
Minimum delay times also represent minimum output hold times.
The transmit delay enable (DXENA) feature of the McBSP is not implemented on the TMS320VC5407/TMS320VC5404.
t
c(BCKRX)
t
w(BCKRXH)
t
t
r(BCKRX)
f(BCKRX)
t
w(BCKRXL)
BCLKR
BFSR (int)
BFSR (ext)
BDR
t
d(BCKRH-BFRV)
t
d(BCKRH-BFRV)
t
su(BFRH-BCKRL)
t
h(BCKRL-BFRH)
t
su(BDRV-BCKRL)
t
h(BCKRL-BDRV)
(n-2)
(n-3)
Bit(n-1)
Figure 5−21. McBSP Receive Timings
93
November 2001 − Revised April 2004
SPRS007D
TI [ TEXAS INSTRUMENTS ]
