欢迎访问ic37.com |
会员登录 免费注册
发布采购

TMS320VC5407 参数 Datasheet PDF下载

TMS320VC5407图片预览
型号: TMS320VC5407
PDF下载: 下载PDF文件 查看货源
内容描述: 定点数字信号处理器 [Fixed-Point Digital Signal Processors]
分类和应用: 数字信号处理器
文件页数/大小: 110 页 / 1351 K
品牌: TI [ TEXAS INSTRUMENTS ]
 浏览型号TMS320VC5407的Datasheet PDF文件第92页浏览型号TMS320VC5407的Datasheet PDF文件第93页浏览型号TMS320VC5407的Datasheet PDF文件第94页浏览型号TMS320VC5407的Datasheet PDF文件第95页浏览型号TMS320VC5407的Datasheet PDF文件第97页浏览型号TMS320VC5407的Datasheet PDF文件第98页浏览型号TMS320VC5407的Datasheet PDF文件第99页浏览型号TMS320VC5407的Datasheet PDF文件第100页  
Electrical Specifications  
5.14.3 McBSP as SPI Master or Slave Timing  
Table 525 to Table 532 assume testing over recommended operating conditions (see Figure 524,  
Figure 525, Figure 526, and Figure 527).  
Table 525. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)  
MASTER  
SLAVE  
UNIT  
MIN  
12  
4
MAX  
MIN  
MAX  
t
t
Setup time, BDR valid before BCLKX low  
Hold time, BDR valid after BCLKX low  
2 6P  
ns  
ns  
su(BDRV-BCKXL)  
5 + 12P  
h(BCKXL-BDRV)  
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.  
P = 0.5 * processor clock  
Table 526. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)  
§
MASTER  
SLAVE  
PARAMETER  
UNIT  
MIN  
MAX  
MIN  
MAX  
t
t
t
Hold time, BFSX low after BCLKX low  
T 3 T + 4  
C 4 C + 3  
ns  
ns  
ns  
h(BCKXL-BFXL)  
d(BFXL-BCKXH)  
d(BCKXH-BDXV)  
#
Delay time, BFSX low to BCLKX high  
Delay time, BCLKX high to BDX valid  
4  
5
6P + 2  
10P + 17  
Disable time, BDX high impedance following last data bit from  
BCLKX low  
t
C 2 C + 3  
ns  
dis(BCKXL-BDXHZ)  
Disable time, BDX high impedance following last data bit from  
BFSX high  
t
t
2P4  
6P + 17  
ns  
ns  
dis(BFXH-BDXHZ)  
Delay time, BFSX low to BDX valid  
4P+ 2  
8P + 17  
d(BFXL-BDXV)  
§
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.  
P = 0.5 * processor clock  
T
C
=
=
BCLKX period = (1 + CLKGDV) * 2P  
BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even  
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX  
and BFSR is inverted before being used internally.  
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP  
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP  
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock  
(BCLKX).  
#
MSB  
LSB  
BCLKX  
BFSX  
t
h(BCKXL-BFXL)  
t
d(BFXL-BCKXH)  
t
dis(BFXH-BDXHZ)  
t
d(BFXL-BDXV)  
t
t
d(BCKXH-BDXV)  
dis(BCKXL-BDXHZ)  
BDX  
BDR  
Bit 0  
Bit(n-1)  
(n-2)  
(n-3)  
(n-4)  
t
su(BDRV-BCLXL)  
t
h(BCKXL-BDRV)  
Bit 0  
Bit(n-1)  
(n-2)  
(n-3)  
(n-4)  
Figure 524. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0  
96  
SPRS007D  
November 2001 Revised April 2004  
 
 复制成功!