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TMS320VC5407 参数 Datasheet PDF下载

TMS320VC5407图片预览
型号: TMS320VC5407
PDF下载: 下载PDF文件 查看货源
内容描述: 定点数字信号处理器 [Fixed-Point Digital Signal Processors]
分类和应用: 数字信号处理器
文件页数/大小: 110 页 / 1351 K
品牌: TI [ TEXAS INSTRUMENTS ]
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Electrical Specifications  
5.7.2 Multiply-By-N Clock Option (PLL Enabled)  
The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to  
generate the internal machine cycle. The selection of the clock mode and the value of N is described in  
Section 3.10. Following reset, the software PLL can be programmed for the desired multiplication factor. Refer  
to the TMS320C54x DSP Reference Set, Volume 1: CPU and Peripherals (literature number SPRU131) for  
detailed information on programming the PLL.  
When an external clock source is used, the external frequency injected must conform to specifications listed  
in Table 56.  
Table 56 and Table 57 assume testing over recommended operating conditions and H = 0.5t  
Figure 54).  
(see  
c(CO)  
Table 56. Multiply-By-N Clock Option Timing Requirements  
MIN  
20  
MAX  
UNIT  
Integer PLL multiplier N (N = 115)  
200  
100  
50  
PLL multiplier N = x.5  
20  
t
Cycle time, X2/CLKIN  
ns  
c(CI)  
PLL multiplier N = x.25, x.75  
20  
t
t
t
t
Fall time, X2/CLKIN  
4
4
ns  
ns  
ns  
ns  
f(CI)  
Rise time, X2/CLKIN  
r(CI)  
Pulse duration, X2/CLKIN low  
Pulse duration, X2/CLKIN high  
4
4
w(CIL)  
w(CIH)  
N is the multiplication factor.  
Table 57. Multiply-By-N Clock Option Switching Characteristics  
PARAMETER  
MIN  
8.33  
4
TYP  
MAX  
UNIT  
ns  
t
Cycle time, CLKOUT  
c(CO)  
t
Delay time, X2/CLKIN high/low to CLKOUT high/low  
Fall time, CLKOUT  
7
2
11  
ns  
d(CI-CO)  
t
ns  
f(CO)  
r(CO)  
w(COL)  
w(COH)  
p
t
t
t
t
Rise time, CLKOUT  
2
ns  
Pulse duration, CLKOUT low  
Pulse duration, CLKOUT high  
Transitory phase, PLL lock-up time  
H
H
ns  
ns  
30  
ms  
t
t
f(CI)  
w(CIH)  
t
r(CI)  
t
t
c(CI)  
w(CIL)  
X2/CLKIN  
t
d(CI-CO)  
t
f(CO)  
t
w(COH)  
t
c(CO)  
t
w(COL)  
t
tp  
r(CO)  
Unstable  
CLKOUT  
NOTE A: The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured as 00 (CLKOUT not  
divided). DIVFCT is configured as CLKOUT divided-by-4 mode following reset.  
Figure 54. Multiply-by-One Clock Timing  
75  
November 2001 Revised April 2004  
SPRS007D  
 
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