Electrical Specifications
5.8 Memory and Parallel I/O Interface Timing
5.8.1 Memory Read
External memory reads can be performed in consecutive or nonconsecutive mode under control of the
CONSEC bit in the BSCR. Table 5−8 and Table 5−9 assume testing over recommended operating conditions
with MSTRB = 0 and H = 0.5t
(see Figure 5−5 and Figure 5−6).
c(CO)
Table 5−8. Memory Read Timing Requirements
MIN
MAX
UNIT
For accesses not immediately following a
HOLD operation
4H−9
ns
Access time, read data access from address
valid, first read access
t
a(A)M1
†
For read accesses immediately following a
HOLD operation
4H−11
2H−9
ns
†
t
t
t
Access time, read data access from address valid, consecutive read accesses
Setup time, read data valid before CLKOUT low
ns
ns
ns
a(A)M2
su(D)R
h(D)R
7
0
Hold time, read data valid after CLKOUT low
†
Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.
Table 5−9. Memory Read Switching Characteristics
PARAMETER
MIN
MAX
UNIT
For accesses not immediately following a
HOLD operation
− 1
4
ns
†
t
Delay time, CLKOUT low to address valid
d(CLKL-A)
For read accesses immediately following a
HOLD operation
− 1
6
ns
t
Delay time, CLKOUT low to MSTRB low
Delay time, CLKOUT low to MSTRB high
− 1
4
4
ns
ns
d(CLKL-MSL)
t
0
d(CLKL-MSH)
†
Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.
76
SPRS007D
November 2001 − Revised April 2004
TI [ TEXAS INSTRUMENTS ]
