Electrical Specifications
5.8.2 Memory Write
Table 5−10 assumes testing over recommended operating conditions with MSTRB = 0 and H = 0.5t
(see
c(CO)
Figure 5−7).
Table 5−10. Memory Write Switching Characteristics
PARAMETER
MIN
MAX
UNIT
For accesses not immediately following a
− 1
4
ns
ns
ns
ns
HOLD operation
Delay time, CLKOUT low to address
valid
t
d(CLKL-A)
†
For read accesses immediately following a
HOLD operation
− 1
2H − 3
2H − 5
6
For accesses not immediately following a
HOLD operation
Setup time, address valid before MSTRB
low
t
su(A)MSL
†
For read accesses immediately following a
HOLD operation
t
Delay time, CLKOUT low to data valid
Setup time, data valid before MSTRB high
Hold time, data valid after MSTRB high
Delay time, CLKOUT low to MSTRB low
Pulse duration, MSTRB low
− 1
2H − 5
2H − 5
− 1
5
2H + 6
2H + 6
4
ns
ns
ns
ns
ns
ns
d(CLKL-D)W
t
su(D)MSH
t
h(D)MSH
t
d(CLKL-MSL)
t
2H − 2
0
w(SL)MS
t
Delay time, CLKOUT low to MSTRB high
4
d(CLKL-MSH)
†
Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
79
November 2001 − Revised April 2004
SPRS007D
TI [ TEXAS INSTRUMENTS ]
