Electrical Specifications
Table 5−4 and Table 5−5 assume testing over recommended operating conditions and H = 0.5t
(see
c(CO)
Figure 5−3).
Table 5−4. Divide-By-2 and Divide-by-4 Clock Options Timing Requirements
MIN
MAX
UNIT
t
t
t
t
t
Cycle time, X2/CLKIN
20
ns
ns
ns
ns
ns
c(CI)
Fall time, X2/CLKIN
4
4
f(CI)
Rise time, X2/CLKIN
r(CI)
Pulse duration, X2/CLKIN low
Pulse duration, X2/CLKIN high
4
4
w(CIL)
w(CIH)
Table 5−5. Divide-By-2 and Divide-by-4 Clock Options Switching Characteristics
PARAMETER
MIN
TYP
MAX
UNIT
ns
†
‡
t
Cycle time, CLKOUT
8.33
c(CO)
t
Delay time, X2/CLKIN high to CLKOUT high/low
Fall time, CLKOUT
4
7
1
11
ns
d(CIH-CO)
t
ns
f(CO)
t
t
t
Rise time, CLKOUT
1
ns
r(CO)
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
H − 3
H − 3
H
H
H + 3
H + 3
ns
w(COL)
w(COH)
ns
†
‡
It is recommended that the PLL clocking option be used for maximum frequency operation.
This device utilizes a fully static design and therefore can operate with t
approaching 0 Hz.
approaching ∞. The device is characterized at frequencies
c(CI)
t
r(CI)
t
w(CIH)
t
t
f(CI)
w(CIL)
t
c(CI)
X2/CLKIN
t
w(COH)
t
f(CO)
t
c(CO)
t
r(CO)
t
d(CIH-CO)
t
w(COL)
CLKOUT
NOTE A: The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured as 00 (CLKOUT not
divided). DIVFCT is configured as CLKOUT divided-by-4 mode following reset.
Figure 5−3. External Divide-by-Two Clock Timing
74
SPRS007D
November 2001 − Revised April 2004
TI [ TEXAS INSTRUMENTS ]
