Electrical Specifications
5.3 Electrical Characteristics Over Recommended Operating Case Temperature
Range (Unless Otherwise Noted)
†
PARAMETER
TEST CONDITIONS
MIN
2.4
TYP
MAX
UNIT
DV = 3 V to 3.6 V, I = MAX
DD
OH
‡
V
V
High-level output voltage
V
OH
DV = 2.7 V to 3 V, I = MAX
2.2
DD
OH
‡
Low-level output voltage
I
OL
= MAX
0.4
V
OL
Input current in high
impedance
I
A[22:0]
DV = MAX, V = DV to DV
DD
−275
275
µA
µA
IZ
DD
O
SS
X2/CLKIN
−40
−10
40
800
400
10
TRST
With internal pulldown
HPIENA
With internal pulldown, RS = 0
With internal pullups
−10
Input current
I
I
§
(V = DV to DV
)
I
SS
DD
TMS, TCK, TDI, HPI
D[15:0], HD[7:0]
−400
−275
−5
µA
Bus holders enabled, DV = MAXk
275
5
DD
All other input-only pins
¶
#
||
I
I
Supply current, core CPU
Supply current, pins
CV = 1.5 V, f = 120 MHz, T = 25°C
42
mA
DDC
DD
x
C
¶
DV = 3.0 V, f = 120 MHz, T = 25°C
20
mA
mA
DDP
DD
x
C
IDLE2
IDLE3
PLL × 1 mode, 20 MHz input
Divide-by-two mode, CLKIN stopped
2
Supply current,
standby
I
DD
1h
mA
C
C
Input capacitance
Output capacitance
5
5
pF
pF
i
o
†
‡
§
¶
#
All values are typical unless otherwise specified.
All input and output voltage levels except RS, INT0−INT3, NMI, X2/CLKIN, CLKMD1−CLKMD3 are LVTTL-compatible.
HPI input signals except for HPIENA.
Clock mode: PLL × 1 with external source
This value was obtained with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program being
executed.
||
This value was obtained with single-cycle external writes, CLKOFF = 0 and load = 15 pF. For more details on how this calculation is performed,
refer to the Calculation of TMS320LC54x Power Dissipation application report (literature number SPRA164).
kV
≤ V ≤ V
or V ≤ V ≤ V
IH(MIN) I IH(MAX)
IL(MIN)
I
IL(MAX)
hMaterial with high I has been observed with an I as high as 7 mA during high temperature testing.
DD
DD
I
OL
50 Ω
Output
Under
Test
Tester Pin
Electronics
V
Load
C
T
I
OH
Where:
I
I
= 1.5 mA (all outputs)
= 300 µA (all outputs)
= 1.5 V
OL
OH
V
Load
C
= 20-pF typical load circuit capacitance
T
Figure 5−1. 3.3-V Test Load Circuit
71
November 2001 − Revised April 2004
SPRS007D