Functional Overview
3.13.1 UART Accessible Registers
The system programmer has access to and control over any of the UART registers that are summarized in
Table 3−14. These registers control UART operations, receive data, and transmit data. Descriptions of these
registers follow Table 3−15. See Table 3−24 for more information on peripheral memory mapped registers.
Table 3−15. Summary of Accessible Registers
UART SUBBANK ADDRESS
0
0
0 (DLAB = 1)
or 8
1
1 (DLAB = 1)
or 9
2
2
3
4
5
6
7
(DLAB = 0)
(DLAB = 0)
(DLAB = 0)
Receiver
Buffer
Register
(Read
Transmitter
Holding
Register
(Write
Interrupt
Ident.
Register
(Read
FIFO
Control
Register
(Write
BIT
NO.
Divisor
Latch
(LSB)
Interrupt
Enable
Register
Divisor
Latch
(MSB)
Line
Control
Register
Modem
Control
Register
Line
Status
Register
Re-
served
Register
Scratch
Register
Only)
Only)
Only)
Only)
RBR
THR
DLL
IER
DLM
IIR
FCR
LCR
MCR
LSR
RSV
SCR
Enable
Received
Data
Available
Interrupt
(ERBI)
Word
Length
Select
Bit 0
0 if
Interrupt
Pending
Data
Ready
(DR)
FIFO
Enable
†
0
Data Bit 0
Data Bit 0
Bit 0
Bit 8
X
X
Bit 0
(WLS0)
Enable
Transmitter
Holding
Register
Empty
Word
Length
Select
Bit 1
Interrupt
ID
Bit 1
Receiver
FIFO
Reset
Overrun
Error
(OE)
1
2
Data Bit 1
Data Bit 2
Data Bit 1
Data Bit 2
Bit 1
Bit 2
Bit 9
X
X
X
X
Bit 1
Bit 2
Interrupt
(ETBEI)
(WLS1)
Enable
Receiver
Line Status
Interrupt
(ELSI)
Number
of
Stop Bits
(STB)
Interrupt
ID
Bit 2
Transmitter
FIFO
Reset
Parity
Error
(PE)
Bit 10
Interrupt
ID
Parity
Enable
(PEN)
Framing
Error
(FE)
‡
0
‡
0
3
4
Data Bit 3
Data Bit 4
Data Bit 3
Data Bit 4
Bit 3
Bit 4
Bit 11
Bit 12
X
X
X
Bit 3
Bit 4
§
Bit 3
Even
Parity
Select
(EPS)
Break
Interrupt
(BI)
0
0
Reserved
Reserved
Loop
Transmitter
Holding
Register
(THRE)
Stick
Parity
‡
0
5
6
Data Bit 5
Data Bit 6
Data Bit 5
Data Bit 6
Bit 5
Bit 6
0
0
Bit 13
Bit 14
0
X
X
Bit 5
Bit 6
Receiver
Trigger
(LSB)
Transmitter
Empty
(TEMT)
FIFOs
Break
Control
0
§
Enabled
Divisor
Latch
Access
Bit
Error in
RCVR
Receiver
Trigger
(MSB)
FIFOs
7
Data Bit 7
0
Data Bit 7
0
Bit 7
0
0
0
Bit 15
0
0
0
X
0
Bit 7
0
§
Enabled
§
FIFO
(DLAB)
8 − 15
0
0
0
0
†
‡
§
Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
Must always be written as zero.
These bits are always 0 in the TL16C450 mode.
NOTE: X = Don’t care for write, indeterminate on read.
52
SPRS007D
November 2001 − Revised April 2004
TI [ TEXAS INSTRUMENTS ]
