Functional Overview
Table 3−13. DMA/CPU Channel Interrupt Selection
INT0SEL VALUE
IMR/IFR[6]
BRINT2
BRINT2
DMAC0
IMR/IFR[7]
BXINT2
IMR/IFR[10]
BRINT1
IMR/IFR[11]
00b (reset)
01b
BXINT1
DMAC3
DMAC3
BXINT2
DMAC2
10b
DMAC1
DMAC2
11b
Reserved
3.13 Universal Asynchronous Receiver/Transmitter (UART)
The UART peripheral is based on the industry-standard TL16C550B asynchronous communications element,
which in turn is a functional upgrade of the TL16C450. Functionally similar to the TL16C450 on power up
(character or TL16C450 mode), the UART can be placed in an alternate FIFO (TL16C550) mode. This relieves
the CPU of excessive software overhead by buffering received and transmitted characters. The receiver and
transmitter FIFOs store up to 16 bytes including three additional bits of error status per byte for the receiver FIFO.
The UART performs serial-to-parallel conversions on data received from a peripheral device or modem and
parallel-to-serial conversion on data received from the CPU. The CPU can read the UART status at any time.
The UART includes control capability and a processor interrupt system that can be tailored to minimize software
management of the communications link.
The UART includes a programmable baud rate generator capable of dividing the CPU clock by divisors from
1 to 65535 and producing a 16× reference clock for the internal transmitter and receiver logic. See Section 5.16
for detailed timing specifications for the UART.
49
November 2001 − Revised April 2004
SPRS007D
TI [ TEXAS INSTRUMENTS ]
