Functional Overview
Table 3−14. UART Reset Functions
REGISTER/SIGNAL
Interrupt enable register
RESET CONTROL
RESET STATE
Master reset
All bits cleared (0−3 forced and 4−7 permanent)
Bit 0 is set, bits 1, 2, 3, 6, and 7 are cleared, and bits 4−5 are
permanently cleared
Interrupt identification register
Master reset
FIFO control register
Line control register
Master reset
Master reset
All bits cleared
All bits cleared
Modem control register
Line status register
Master reset
All bits cleared (6−7 permanent)
Master reset
Bits 5 and 6 are set; all other bits are cleared
Reserved register
Master reset
Indeterminate
High
SOUT
Master reset
INTRPT (receiver error flag)
INTRPT (received data available)
INTRPT (transmitter holding register empty)
Scratch register
Read LSR/MR
Read RBR/MR
Read IR/write THR/MR
Master reset
Low
Low
Low
No effect
No effect
No effect
No effect
Divisor latch (LSB and MSB) registers
Receiver buffer register
Transmitter holding register
RCVR FIFO
Master reset
Master reset
Master reset
MR/FCR1−FCR0/∆FCR0 All bits cleared
MR/FCR2−FCR0/∆FCR0 All bits cleared
XMIT FIFO
51
November 2001 − Revised April 2004
SPRS007D
TI [ TEXAS INSTRUMENTS ]
