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TMS320VC5407 参数 Datasheet PDF下载

TMS320VC5407图片预览
型号: TMS320VC5407
PDF下载: 下载PDF文件 查看货源
内容描述: 定点数字信号处理器 [Fixed-Point Digital Signal Processors]
分类和应用: 数字信号处理器
文件页数/大小: 110 页 / 1351 K
品牌: TI [ TEXAS INSTRUMENTS ]
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Functional Overview  
3.12.10 DMA Interrupts  
The ability of the DMA to interrupt the CPU based on the status of the data transfer is configurable and is  
determined by the IMOD and DINM bits in the DMA transfer mode control register (DMMCRn). The available  
modes are shown in Table 311.  
Table 311. DMA Interrupts  
MODE  
ABU (non-decrement)  
ABU (non-decrement)  
Multi frame  
DINM  
IMOD  
INTERRUPT  
1
1
1
1
0
0
0
1
0
1
X
X
At full buffer only  
At half buffer and full buffer  
At block transfer complete (DMCTRn = DMSEFCn[7:0] = 0)  
At end of frame and end of block (DMCTRn = 0)  
No interrupt generated  
Multi frame  
Either  
Either  
No interrupt generated  
3.12.11 DMA Controller Synchronization Events  
The transfers associated with each DMA channel can be synchronized to one of several events. The DSYN  
bit field of the DMSEFCn register selects the synchronization event for a channel. The list of possible events  
and the DSYN values are shown in Table 312.  
Table 312. DMA Synchronization Events  
DSYN VALUE  
0000b  
0001b  
0010b  
0011b  
0100b  
0101b  
0110b  
0111b  
DMA SYNCHRONIZATION EVENT  
No synchronization used  
McBSP0 receive event  
McBSP0 transmit event  
McBSP2 receive event  
McBSP2 transmit event  
McBSP1 receive event  
McBSP1 transmit event  
UART  
1000b  
1001b  
1010b  
1011b  
1100b  
1101b  
1110b  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Timer 0 interrupt event  
External interrupt 3  
Timer 1 interrupt event  
1111b  
Note that the UART DMA synchronization event is usable as a synchronization event only, and is not usable  
for transferring data to or from the UART. The DMA cannot be used to transfer data to or from the UART.  
The DMA controller can generate a CPU interrupt for each of the six channels. However, due to a limit on the  
number of internal CPU interrupt inputs, channels 0, 1, 2, and 3 are multiplexed with other interrupt sources.  
DMA channels 0, 1, 2, and 3 share an interrupt line with the receive and transmit portions of the McBSP. When  
the 5407/5404 is reset, the interrupts from these three DMA channels are deselected. The INT0SEL bit field  
in the DMPREC register can be used to select these interrupts, as shown in Table 313.  
48  
SPRS007D  
November 2001 Revised April 2004  
 
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