Functional Overview
Table 3−19. Number of Stop Bits Generated
WORD LENGTH SELECTED
BY BITS 1 AND 2
NUMBER OF STOP
BITS GENERATED
BIT 2
0
1
1
1
1
Any word length
5 bits
1
1 1/2
2
6 bits
7 bits
2
8 bits
2
•
•
•
•
•
Bit 3: This bit is the parity enable bit. When bit 3 is set, a parity bit is generated in transmitted data between
the last data word bit and the first stop bit. In received data, if bit 3 is set, parity is checked. When bit 3 is
cleared, no parity is generated or checked.
Bit 4: This bit is the even parity select bit. When parity is enabled (bit 3 is set) and bit 4 is set even parity
(an even number of logic 1s in the data and parity bits) is selected. When parity is enabled and bit 4 is
cleared, odd parity (an odd number of logic 1s) is selected.
Bit 5: This bit is the stick parity bit. When bits 3, 4, and 5 are set, the parity bit is transmitted and checked
as cleared. When bits 3 and 5 are set and bit 4 is cleared, the parity bit is transmitted and checked as set.
If bit 5 is cleared, stick parity is disabled.
Bit 6: This bit is the break control bit. Bit 6 is set to force a break condition; i.e., a condition where SOUT
is forced to the spacing (cleared) state. When bit 6 is cleared, the break condition is disabled and has no
affect on the transmitter logic; it only effects SOUT.
Bit 7: This bit is the divisor latch access bit (DLAB). Bit 7 must be set to access the divisor latches of the
baud generator during a read or write. Bit 7 must be cleared during a read or write to access the receiver
buffer, the THR, or the IER.
3.13.8 Line Status Register (LSR)†
The LSR provides information to the CPU concerning the status of data transfers. The contents of this register
are summarized in Table 3−15 and described in the following bulleted list.
•
Bit 0: This bit is the data ready (DR) indicator for the receiver. DR is set whenever a complete incoming
character has been received and transferred into the RBR or the FIFO. DR is cleared by reading all of the
data in the RBR or the FIFO.
‡
•
Bit 1 : This bit is the overrun error (OE) indicator. When OE is set, it indicates that before the character in
the RBR was read, it was overwritten by the next character transferred into the register. OE is cleared every
time the CPU reads the contents of the LSR. If the FIFO mode data continues to fill the FIFO beyond the
trigger level, an overrun error occurs only after the FIFO is full and the next character has been completely
received in the shift register. An overrun error is indicated to the CPU as soon as it happens. The character
in the shift register is overwritten, but it is not transferred to the FIFO.
‡
•
•
Bit 2 : This bit is the parity error (PE) indicator. When PE is set, it indicates that the parity of the received
data character does not match the parity selected in the LCR (bit 4). PE is cleared every time the CPU reads
the contents of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO
to which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO.
‡
Bit 3 : This bit is the framing error (FE) indicator. When FE is set, it indicates that the received character
did not have a valid (set) stop bit. FE is cleared every time the CPU reads the contents of the LSR. In the
FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This error
is revealed to the CPU when its associated character is at the top of the FIFO. The UART tries to
resynchronize after a framing error. To accomplish this, it is assumed that the framing error is due to the next
start bit. The UART samples this start bit twice and then accepts the input data.
†
‡
The line status register is intended for read operations only; writing to this register is not recommended.
Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.
56
SPRS007D
November 2001 − Revised April 2004
TI [ TEXAS INSTRUMENTS ]
