Functional Overview
Data Space (0000 − 005F)
Data Space
I/O Space
Hex
Hex
0000
0000
001F
0020
0021
0022
0000
Reserved
Data Space
(See Breakout)
DRR20
DRR10
DXR20
005F
0060
0023
0024
002F
0030
0031
0032
0033
DXR10
Scratch-Pad
RAM
Reserved
DRR22
DRR12
DXR22
DXR12
007F
0080
On-Chip
DARAM0
8K Words
1FFF
2000
On-Chip
DARAM1
8K Words
0034
3FFF
4000
On-Chip
†
DARAM2
Reserved
8K Words
Reserved
5FFF
6000
On-Chip
†
DARAM3
8K Words
003F
0040
0041
0042
0043
0044
7FFF
8000
DRR21
On-Chip
†
DRR11
DXR21
DXR11
DARAM4
8K Words
9FFF
A000
Reserved
Reserved
005F
FFFF
FFFF
†
Reserved on the 5404
Figure 3−20. On-Chip DMA Memory Map for Data and IO Space (DLAXS = 0 and SLAXS = 0)
3.12.4 DMA Priority Level
Each DMA channel can be independently assigned high- or low-priority relative to each other. Multiple DMA
channels that are assigned to the same priority level are handled in a round-robin manner.
3.12.5 DMA Source/Destination Address Modification
The DMA provides flexible address-indexing modes for easy implementation of data management schemes
such as autobuffering and circular buffers. Source and destination addresses can be indexed separately and
can be post-incremented, post-decremented, or post-incremented with a specified index offset.
3.12.6 DMA in Autoinitialization Mode
The DMA can automatically reinitialize itself after completion of a block transfer. Some of the DMA registers
can be preloaded for the next block transfer through the DMA reload registers (DMGSA, DMGDA, DMGCR,
and DMGFR). Autoinitialization allows:
•
Continuous operation: Normally, the CPU would have to reinitialize the DMA immediately after the
completion of the current block transfers, but with the reload registers, it can reinitialize these values for
the next block transfer any time after the current block transfer begins.
•
Repetitive operation:The CPU does not preload the reload register with new values for each block transfer
but only loads them on the first block transfer.
46
SPRS007D
November 2001 − Revised April 2004
TI [ TEXAS INSTRUMENTS ]
