Peripherals
If configured for ”Digital I/O” mode, additional registers are provided for setting individual I/O signals (via the
GPxSET registers), for clearing individual I/O signals (via the GPxCLEAR registers), for toggling individual I/O
signals (via the GPxTOGGLE registers), or for reading/writing to the individual I/O signals (via the GPxDAT
registers). Table 4−12 lists the GPIO Data Registers. For more information, see the TMS320x281x System
Control and Interrupts Reference Guide (literature number SPRU078).
†‡
Table 4−12. GPIO Data Registers
NAME
GPADAT
ADDRESS
0x00 70E0
0x00 70E1
0x00 70E2
0x00 70E3
0x00 70E4
0x00 70E5
0x00 70E6
0x00 70E7
0x00 70E8
0x00 70E9
0x00 70EA
0x00 70EB
0x00 70EC
0x00 70ED
0x00 70EE
0x00 70EF
0x00 70F0
0x00 70F1
0x00 70F2
0x00 70F3
0x00 70F4
0x00 70F5
0x00 70F6
0x00 70F7
0x00 70F8
0x00 70F9
0x00 70FA
0x00 70FB
SIZE (x16)
REGISTER DESCRIPTION
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GPIO A Data Register
GPIO A Set Register
GPASET
GPACLEAR
GPATOGGLE
GPBDAT
GPIO A Clear Register
GPIO A Toggle Register
GPIO B Data Register
GPIO B Set Register
GPIO B Clear Register
GPIO B Toggle Register
GPBSET
GPBCLEAR
GPBTOGGLE
reserved
reserved
reserved
reserved
GPDDAT
GPIO D Data Register
GPIO D Set Register
GPIO D Clear Register
GPIO D Toggle Register
GPIO E Data Register
GPIO E Set Register
GPIO E Clear Register
GPIO E Toggle Register
GPIO F Data Register
GPIO F Set Register
GPIO F Clear Register
GPIO F Toggle Register
GPIO G Data Register
GPIO G Set Register
GPIO G Clear Register
GPIO G Toggle Register
GPDSET
GPDCLEAR
GPDTOGGLE
GPEDAT
GPESET
GPECLEAR
GPETOGGLE
GPFDAT
GPFSET
GPFCLEAR
GPFTOGGLE
GPGDAT
GPGSET
GPGCLEAR
GPGTOGGLE
0x00 70FC
0x00 70FF
reserved
4
†
‡
Reserved locations will return undefined values and writes will be ignored.
These registers are NOT EALLOW protected. The above registers will typically be accessed regularly by the user.
84
SPRS174L
April 2001 − Revised December 2004
TI [ TEXAS INSTRUMENTS ]
