Peripherals
4.8
GPIO MUX
The GPIO Mux registers, are used to select the operation of shared pins on the F281x and C281x devices.
The pins can be individually selected to operate as “Digital I/O” or connected to “Peripheral I/O” signals (via
the GPxMUX registers). If selected for “Digital I/O” mode, registers are provided to configure the pin direction
(via the GPxDIR registers) and to qualify the input signal to remove unwanted noise (via the GPxQUAL)
registers). Table 4−11 lists the GPIO Mux Registers.
†‡§
Table 4−11. GPIO Mux Registers
NAME
GPAMUX
GPADIR
GPAQUAL
reserved
GPBMUX
GPBDIR
GPBQUAL
reserved
reserved
reserved
reserved
reserved
GPDMUX
GPDDIR
GPDQUAL
reserved
GPEMUX
GPEDIR
GPEQUAL
reserved
GPFMUX
GPFDIR
reserved
reserved
GPGMUX
GPGDIR
reserved
reserved
ADDRESS
0x00 70C0
0x00 70C1
0x00 70C2
0x00 70C3
0x00 70C4
0x00 70C5
0x00 70C6
0x00 70C7
0x00 70C8
0x00 70C9
0x00 70CA
0x00 70CB
0x00 70CC
0x00 70CD
0x00 70CE
0x00 70CF
0x00 70D0
0x00 70D1
0x00 70D2
0x00 70D3
0x00 70D4
0x00 70D5
0x00 70D6
0x00 70D7
0x00 70D8
0x00 70D9
0x00 70DA
0x00 70DB
SIZE (x16)
REGISTER DESCRIPTION
GPIO A Mux Control Register
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GPIO A Direction Control Register
GPIO A Input Qualification Control Register
GPIO B Mux Control Register
GPIO B Direction Control Register
GPIO B Input Qualification Control Register
GPIO D Mux Control Register
GPIO D Direction Control Register
GPIO D Input Qualification Control Register
GPIO E Mux Control Register
GPIO E Direction Control Register
GPIO E Input Qualification Control Register
GPIO F Mux Control Register
GPIO F Direction Control Register
GPIO G Mux Control Register
GPIO G Direction Control Register
0x00 70DC
0x00 70DF
reserved
4
†
‡
§
Reserved locations will return undefined values and writes will be ignored.
Not all inputs will support input signal qualification.
These registers are EALLOW protected. This prevents spurious writes from overwriting the contents and corrupting the system.
83
April 2001 − Revised December 2004
SPRS174L