ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉꢄ ꢅ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢇꢍꢂ ꢂꢑ ꢖ
SPRS080F − MARCH 1999 − REVISED OCTOBER 2008
interrupts (continued)
Figure 9 shows the bit layout of the interrupt mask register (IMR) and the interrupt flag register (IFR). Table 14
describes the bit functions.
The interprocessor interrupt (IPINT) bit of the interrupt mask register (IMR) and the interrupt flag register (IFR)
allows the subsystem to perform interrupt service routines based on the other subsystem activity. Incoming
IPINT interrupts are latched in bit 14 of the IFR. Generating an interprocessor interrupt is performed by writing
a “1” to the IPIRQ field of the bank-switching control register (BSCR). Subsequent interrupts must first clear the
interrupt by writing “0” to the IPIRQ field.
For example, if subsystem A is required to notify subsystem B of a completed task, subsystem A must write a
“1” to the IPIRQ field to generate a IPINT interrupt on subsystem B. On subsystem B, the IPINT interrupt is
latched in bit 14 of the IFR.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IPINT
DMAC5
DMAC4
BXINT1 BRINT1 HPINT
or or
DMAC3 DMAC2
RES
BXINT2 BRINT2 BXINT0 BRINT0 TINT
or or
DMAC1 DMAC0
RES
INT1
INT0
RES
Figure 9. Bit Layout of the IMR and IFR Registers for Each Subsystem
Table 14. Bit Functions for IMR and IFR Registers for Each DSP Subsystem
BIT
FUNCTION
NUMBER
NAME
15
14
13
12
−
Reserved
IPINT
Interprocessor IRQ.
DMAC5
DMAC4
DMA channel 5 interrupt flag/mask bit
DMA channel 4 interrupt flag/mask bit
This bit can be configured as either the McBSP1 transmit interrupt flag/mask bit, or the DMA
channel 3 interrupt flag/mask bit. The selection is made in the DMPREC register.
11
10
BXINT1/DMAC3
BRINT1/DMAC2
This bit can be configured as either the McBSP1 receive interrupt flag/mask bit, or the DMA
channel 2 interrupt flag/mask bit. The selection is made in the DMPREC register.
9
8
HPINT
−
Host to 54x interrupt flag/mask
Reserved
This bit can be configured as either the McBSP2 transmit interrupt flag/mask bit, or the DMA
channel 1 interrupt flag/mask bit. The selection is made in the DMPREC register.
7
6
BXINT2/DMAC1
BRINT2/DMAC0
This bit can be configured as either the McBSP2 receive interrupt flag/mask bit, or the DMA
channel 0 interrupt flag/mask bit. The selection is made in the DMPREC register.
5
4
3
2
1
0
BXINT0
BRINT0
TINT
−
McBSP0 transmit interrupt flag/mask bit
McBSP0 receive interrupt flag/mask bit
Timer interrupt flag/mask bit
Reserved
INT1
INT0
External interrupt 1 flag/mask bit
External interrupt 0 flag/mask bit
38
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