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SPRS080F − MARCH 1999 − REVISED OCTOBER 2008
electrical characteristics over recommended operating case temperature range (unless otherwise
noted)
†
TYP
PARAMETER
TEST CONDITIONS
= 3.3 0.3 V, I = MAX
MIN
MAX
UNIT
V
‡
V
V
High-level output voltage
DV
2.4
OH
DD
DD
OH
‡
Low-level output voltage
I
= MAX
0.4
10
35
10
V
OL
OL
I
IZ
Input current in high impedance
TRST
DV
= MAX, V = V
SS
to DV
DD
−10
−10
−35
µA
O
With internal pulldown
With internal pullups
See pin descriptions
Input current
(V = V to
I
I
Bus holders enabled, DV
= MAX,
µA
I
SS
DD
PPD[15:0]
−200
−10
200
10
V
)
V = V
SS
to V (MAX); V (MIN) to DV
IL IH DD
DD
I
All other input-only pins
§
¶
I
I
I
Supply current, both core CPUs
Supply current, pins
CV
DV
= 1.8 V, f =100 MHz , T =25°C
180
54
5
mA
mA
mA
mA
µA
DDC
DDP
DDA
DD
DD
x
C
¶
#
= 3.3 V, f
= 100 MHz , T = 25°C
C
clock
Supply current, PLL
IDLE2
IDLE3
PLL × n mode, 20 MHz input
2
Supply current,
standby
I
DDC
PLL x n mode, 20 MHz input
600
5
C
C
Input capacitance
Output capacitance
pF
i
5
pF
o
†
‡
All values are typical unless otherwise specified.
All input and output voltage levels except A_RS, B_RS, INT0 INT1, NMI, CLKIN, BCLKX, BCLKR, HAS, HCS, TCK, TRST, SELA/B, HDS1,
HDS2, and HPIRS are LVTTL-compatible.
§
¶
Clock mode: PLL × 1 with external source
This value represents the current consumption of the CPU, on-chip memory, and on-chip peripherals. Conditions include: program execution
from on-chip RAM, with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program being executed.
This value was obtained using the following conditions: external memory writes at a rate of 20 million writes per second, CLKOFF=0, full-duplex
operation of all six McBSPs at a rate of 10 million bits per second each, and 15-pF loads on all outputs. For more details on how this calculation
is performed, refer to the Calculation of TMS320C54x Power Dissipation Application Report (literature number SPRA164).
#
PARAMETER MEASUREMENT INFORMATION
I
OL
50 Ω
Output
Under
Test
Tester Pin
Electronics
V
Load
C
T
I
OH
Where:
I
I
V
=
=
=
=
1.5 mA (all outputs)
300 µA (all outputs)
1.5 V
OL
OH
Load
T
C
40 pF typical load circuit capacitance
Figure 10. 3.3-V Test Load Circuit
42
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