TMS320VC5402
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
multiply-by-N clock option
The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to generate
the internal machine cycle. The selection of the clock mode and the value of N is described in the clock generator
section.
When an external clock source is used, the external frequency injected must conform to specifications listed
in the timing requirements table.
NOTE:
All revisions of the ’5402 can be operated with an external clock source, provided that the proper
voltage levels be driven on the X2/CLKIN pin. It should be noted that the X2/CLKIN pin is referenced to
the device 1.8V power supply (CVdd), rather than the 3V I/O supply (DVdd). Refer to the recommended
operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.
timing requirements (see Figure 12)
†
Integer PLL multiplier N (N = 1–15)
tc(CI)
Cycle time, X2/CLKIN
PLL multiplier N = x.5
PLL multiplier N = x.25, x.75
MIN
20‡
20‡
20‡
MAX
200
100
50
ns
UNIT
tf(CI)
Fall time, X2/CLKIN
8
ns
tr(CI)
Rise time, X2/CLKIN
8
ns
† N = Multiplication factor
‡ The multiplication factor and minimum X2/CLKIN cycle time should be chosen such that the resulting CLKOUT cycle time is within the specified
range (tc(CO))
switching characteristics over
(see Figure 10 and Figure 12)
tc(CO)
td(CI-CO)
tf(CO)
tr(CO)
tw(COL)
tw(COH)
Cycle time, CLKOUT
recommended
operating
conditions
MIN
10
4
[H
=
0.5t
c(CO)
]
MAX
17
UNIT
ns
ns
ns
ns
H
H
30
ns
ns
ms
PARAMETER
Delay time, X2/CLKIN high/low to CLKOUT high/low
Fall time, CLKOUT
Rise time, CLKOUT
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
TYP
tc(CI)/N†
10
2
2
H–2
H–2
tp
Transitory phase, PLL lock up time
† N = Multiplication factor
tc(CI)
X2/CLKIN
td(CI-CO)
tc(CO)
tp
CLKOUT
Unstable
tw(COH)
tf(CO)
tw(COL)
tr(CO)
tr(CI)
tf(CI)
Figure 12. External Multiply-by-One Clock Timing
38
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