TMS320VC5402
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
memory and parallel I/O interface timing
timing requirements for a
memory read (MSTRB = 0)
[H = 0.5 t
c(CO)
]
†
(see Figure 13)
MIN
ta(A)M
ta(MSTRBL)
tsu(D)R
th(D)R
th(A-D)R
Access time, read data access from address valid
Access time, read data access from MSTRB low
Setup time, read data before CLKOUT low
Hold time, read data after CLKOUT low
Hold time, read data after address invalid
6
–2
0
0
MAX
2H–7
2H–8
UNIT
ns
ns
ns
ns
ns
ns
th(D)MSTRBH Hold time, read data after MSTRB high
† Address, PS, and DS timings are all included in timings referenced as address.
switching characteristics over recommended operating conditions for a
memory read
(MSTRB = 0)
†
(see Figure 13)
td(CLKL-A)
td(CLKH-A)
td(CLKL-MSL)
td(CLKL-MSH)
PARAMETER
Delay time, CLKOUT low to address valid‡
Delay time, CLKOUT high (transition) to address valid§
Delay time, CLKOUT low to MSTRB low
Delay time, CLKOUT low to MSTRB high
MIN
–2
–2
–1
–1
–2
–2
MAX
3
3
3
3
3
3
UNIT
ns
ns
ns
ns
ns
ns
th(CLKL-A)R
Hold time, address valid after CLKOUT low‡
th(CLKH-A)R
Hold time, address valid after CLKOUT high§
† Address, PS, and DS timings are all included in timings referenced as address.
‡ In the case of a memory read preceded by a memory read
§ In the case of a memory read preceded by a memory write
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