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TMS320VC5402ZGU100 参数 Datasheet PDF下载

TMS320VC5402ZGU100图片预览
型号: TMS320VC5402ZGU100
PDF下载: 下载PDF文件 查看货源
内容描述: 定点数字信号处理器 [FIXED-POINT DIGITAL SIGNAL PROCESSOR]
分类和应用: 微控制器和处理器外围集成电路数字信号处理器装置时钟
文件页数/大小: 68 页 / 933 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMS320VC5402
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
divide-by-two clock option (PLL disabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two to generate
the internal machine cycle. The selection of the clock mode is described in the clock generator section.
When an external clock source is used, the frequency injected must conform to specifications listed in the timing
requirements table.
NOTE:
All revisions of the ’5402 can be operated with an external clock source, provided that the proper
voltage levels be driven on the X2/CLKIN pin. It should be noted that the X2/CLKIN pin is referenced to
the device 1.8V power supply (CVdd), rather than the 3V I/O supply (DVdd). Refer to the recommended
operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.
timing requirements (see Figure 11)
MIN
tc(CI)
tf(CI)
Cycle time, X2/CLKIN
Fall time, X2/CLKIN
20
MAX
8
UNIT
ns
ns
tr(CI)
Rise time, X2/CLKIN
8
ns
† This device utilizes a fully static design and therefore can operate with tc(CI) approaching
∞.
The device is characterized at frequencies
approaching 0 Hz.
switching characteristics over recommended operating conditions [H = 0.5t
c(CO)
]
(see Figure 10,
Figure 11, and the recommended operating conditions table)
PARAMETER
tc(CO)
td(CIH-CO)
tf(CO)
tr(CO)
Cycle time, CLKOUT
Delay time, X2/CLKIN high to CLKOUT high/low
Fall time, CLKOUT
Rise time, CLKOUT
MIN
10‡
4
TYP
2tc(CI)
10
2
2
MAX
17
UNIT
ns
ns
ns
ns
tw(COL)
Pulse duration, CLKOUT low
H–2
H
ns
tw(COH)
Pulse duration, CLKOUT high
H–2
H
ns
† This device utilizes a fully static design and therefore can operate with tc(CI) approaching
∞.
The device is characterized at frequencies
approaching 0 Hz.
‡ It is recommended that the PLL clocking option be used for maximum frequency operation.
tr(CI)
tc(CI)
X2/CLKIN
tf(CI)
tc(CO)
td(CIH-CO)
CLKOUT
tf(CO)
tr(CO)
tw(COH)
tw(COL)
Figure 11. External Divide-by-Two Clock Timing
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
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