TMS320VC5402
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
electrical characteristics over recommended operating case temperature range (unless otherwise
noted)
PARAMETER
VOH
VOL
IIZ
High-level output voltage
Low-level output voltage
Input current for D[15:0], HD[7:0]
out uts
outputs in high
impedance
All other inputs
X2/CLKIN
}
TRST
II
Input cu e
u current
HPIENA
TMS, TCK, TDI, HPI
w
All other input-only pins
input only
IDDC
IDDP
IDD
Ci
Supply current, core CPU
Supply current, pins
Su ly
Supply current,
standby
Input capacitance
IDLE2
IDLE3
CVDD = 1.8 V, fclock = 100 MHz¶, TC = 25°C#
DVDD = 3.3 V, fclock = 100 MHz¶, TC = 25°C||
PLL
×
1 mode,
100 MHz input
Divide-by-two mode, CLKIN stopped
With internal pulldown
With internal pulldown
With internal pullups,
HPIENA = 0
(VI = VSS
(
to DVDD)
IOH = MAX
IOL = MAX
Bus holders enabled, DVDD = MAX,
VI = VSS to DVDD
DVDD = MAX, VO = VSS to DVDD
TEST CONDITIONS
MIN
2.4
0.4
–175
–5
–40
–5
–5
–300
5
–5
45
30
2
20
5
175
5
40
300
300
5
5
mA
mA
mA
µA
pF
µA
TYP†
MAX
UNIT
V
V
µA
Co
Output capacitance
5
pF
† All values are typical unless otherwise specified.
‡ All revisions of the ’5402 can be operated with an external clock source, provided that the proper voltage levels be driven on the X2/CLKIN pin.
It should be noted that the X2/CLKIN pin is referenced to the device 1.8V power supply (CVdd), rather than the 3V I/O supply (DVdd). Refer to
the recommended operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.
§ HPI input signals except for HPIENA.
¶ Clock mode: PLL
×
1 with external source
# This value represents the current consumption of the CPU, on-chip memory, and on-chip peripherals. Conditions include: program execution
from on-chip RAM, with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program being executed.
|| This value was obtained using the following conditions: external memory writes at a rate of 20 million writes per second, CLKOFF=0, full-duplex
operation of McBSP0 and McBSP1 at a rate of 10 million bits per second each, and 15-pF loads on all outputs. For more details on how this
calculation is performed, refer to the
Calculation of TMS320C54x Power Dissipation Application Report
(literature number SPRA164).
PARAMETER MEASUREMENT INFORMATION
IOL
50
Ω
Tester Pin
Electronics
VLoad
C
T
Output
Under
Test
IOH
Where:
IOL
IOH
VLoad
CT
=
=
=
=
1.5 mA (all outputs)
300
µA
(all outputs)
1.5 V
40 pF typical load circuit capacitance
Figure 9. 3.3-V Test Load Circuit
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251–1443
35
TI [ TEXAS INSTRUMENTS ]
