SPRS439M – JUNE 2007 – REVISED AUGUST 2012
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3.3-V Test Load Circuit
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Clock Timing
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Power-on Reset
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Warm Reset
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Example of Effect of Writing Into PLLCR Register
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General-Purpose Output Timing
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Sampling Mode
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General-Purpose Input Timing
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IDLE Entry and Exit Timing
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STANDBY Entry and Exit Timing Diagram
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HALT Wake-Up Using GPIOn
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PWM Hi-Z Characteristics
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ADCSOCAO or ADCSOCBO Timing
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External Interrupt Timing
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SPI Master Mode External Timing (Clock Phase = 0)
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SPI Master Mode External Timing (Clock Phase = 1)
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SPI Slave Mode External Timing (Clock Phase = 0)
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SPI Slave Mode External Timing (Clock Phase = 1)
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Relationship Between XTIMCLK and SYSCLKOUT
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Example Read Access
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Example Write Access
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Example Read With Synchronous XREADY Access
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Example Read With Asynchronous XREADY Access
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Write With Synchronous XREADY Access
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Write With Asynchronous XREADY Access
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External Interface Hold Waveform
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XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
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ADC Power-Up Control Bit Timing
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ADC Analog Input Impedance Model
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Sequential Sampling Mode (Single-Channel) Timing
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Simultaneous Sampling Mode Timing
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McBSP Receive Timing
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McBSP Transmit Timing
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McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
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McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
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McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
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McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
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Emulator Connection Without Signal Buffering for the DSP
6
List of Figures
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