SPRS439M – JUNE 2007 – REVISED AUGUST 2012
(A) (B)
WS (Synch)
Active
Lead
Trail
(C)
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
XZCS0 XZCS6, XZCS7
t
d(XCOH-XZCSL)
t
d(XCOH-XA)
XA[0:19]
t
d(XCOHL-XRDL)
XRD
XWE0,
XWE1
(D)
XR/W
t
a(A)
t
h(XD)XRD
XD[0:31], XD[0:15]
t
su(XRDYsynchL)XCOHL
t
e(XRDYsynchH)
t
h(XRDYsynchL)
t
su(XRDHsynchH)XCOHL
XREADY(Synch)
(E)
(F)
t
d(XCOHL-XZCSH)
t
d(XCOHL-XRDH)
t
su(XD)XRD
t
a(XRD)
DIN
t
h(XRDYsynchH)XZCSH
Legend:
= Don’t care. Signal can be high or low during this time.
A.
B.
C.
D.
E.
F.
All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When
necessary,
the device inserts an
alignment cycle before an access to meet this requirement.
During alignment cycles, all signals transition to their inactive state.
During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which
remains high. This includes alignment cycles.
XWE1 is valid only in 32-bit data bus mode. In 16-bit mode, this signal is XA0.
For each sample, setup time from the beginning of the access (E) can be calculated as:
D = (XRDLEAD + XRDACTIVE +n - 1) t
c(XTIM)
– t
su(XRDYsynchL)XCOHL
Reference for the first sample is with respect to this point: F = (XRDLEAD + XRDACTIVE) t
c(XTIM)
where n is the
sample number: n = 1, 2, 3, and so forth.
Figure 6-25. Example Read With Synchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD
≥
1
XRDACTIVE
3
XRDTRAIL
≥
1
USEREADY
1
X2TIMING
0
XWRLEAD
N/A
(1)
XWRACTIVE
N/A
(1)
XWRTRAIL
N/A
(1)
READYMODE
0 = XREADY
(Synch)
(1)
N/A = “Don’t care” for this example
Copyright © 2007–2012, Texas Instruments Incorporated
Electrical Specifications
161
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