SPRS439M – JUNE 2007 – REVISED AUGUST 2012
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
6
7
SPISIMO
Master Out Data Is Valid
10
11
SPISOMI
Master In Data Must
Be Valid
Data Valid
SPISTE
(A)
B.
In the master mode, SPISTE goes active 0.5t
c(SPC)
(minimum) before valid SPI clock edge. On the trailing
end of the word, the SPISTE will go inactive 0.5t
c(SPC)
after the receiving edge (SPICLK) of the last data bit,
except that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes.
Figure 6-19. SPI Master Mode External Timing (Clock Phase = 1)
Copyright © 2007–2012, Texas Instruments Incorporated
Electrical Specifications
147
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