SPRS439M – JUNE 2007 – REVISED AUGUST 2012
Contents
1
TMS320F2833x, TMS320F2823x DSCs
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1.1
1.2
Features
....................................................................................................................
Getting Started
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Pin Assignments
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Signal Descriptions
........................................................................................................
Memory Maps
..............................................................................................................
Brief Descriptions
..........................................................................................................
3.2.1
C28x CPU
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3.2.2
Memory Bus (Harvard Bus Architecture)
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3.2.3
Peripheral Bus
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3.2.4
Real-Time JTAG and Analysis
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3.2.5
External Interface (XINTF)
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3.2.6
Flash
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3.2.7
M0, M1 SARAMs
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3.2.8
L0, L1, L2, L3, L4, L5, L6, L7 SARAMs
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3.2.9
Boot ROM
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3.2.9.1
Peripheral Pins Used by the Bootloader
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3.2.10 Security
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3.2.11 Peripheral Interrupt Expansion (PIE) Block
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3.2.12 External Interrupts (XINT1–XINT7, XNMI)
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3.2.13 Oscillator and PLL
..............................................................................................
3.2.14 Watchdog
........................................................................................................
3.2.15 Peripheral Clocking
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3.2.16 Low-Power Modes
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3.2.17 Peripheral Frames 0, 1, 2, 3 (PFn)
...........................................................................
3.2.18 General-Purpose Input/Output (GPIO) Multiplexer
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3.2.19 32-Bit CPU-Timers (0, 1, 2)
...................................................................................
3.2.20 Control Peripherals
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3.2.21 Serial Port Peripherals
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Register Map
...............................................................................................................
Device Emulation Registers
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Interrupts
....................................................................................................................
3.5.1
External Interrupts
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System Control
............................................................................................................
3.6.1
OSC and PLL Block
............................................................................................
3.6.1.1
External Reference Oscillator Clock Option
....................................................
3.6.1.2
PLL-Based Clock Module
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3.6.1.3
Loss of Input Clock
................................................................................
3.6.2
Watchdog Block
.................................................................................................
Low-Power Modes Block
.................................................................................................
DMA Overview
.............................................................................................................
32-Bit CPU-Timer 0, CPU-Timer 1, CPU-Timer 2
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Enhanced PWM Modules
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High-Resolution PWM (HRPWM)
.......................................................................................
Enhanced CAP Modules
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Enhanced QEP Modules
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Analog-to-Digital Converter (ADC) Module
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4.7.1
ADC Connections if the ADC Is Not Used
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2
Introduction
......................................................................................................................
2.1
2.2
3
Functional Overview
..........................................................................................................
3.1
3.2
3.3
3.4
3.5
3.6
3.7
4
Peripherals
.......................................................................................................................
4.1
4.2
4.3
4.4
4.5
4.6
4.7
2
Contents
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