SPRS174S – APRIL 2001 – REVISED MARCH 2011
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Unless otherwise specified, all XINTF timing is applicable for the clock configurations shown in
Table 6-31. XINTF Clock Configurations
MODE
1
Example:
2
Example:
3
Example:
4
Example:
SYSCLKOUT
150 MHz
150 MHz
150 MHz
150 MHz
XTIMCLK
SYSCLKOUT
150 MHz
SYSCLKOUT
150 MHz
1/2 SYSCLKOUT
75 MHz
1/2 SYSCLKOUT
75 MHz
XCLKOUT
SYSCLKOUT
150 MHz
1/2 SYSCLKOUT
75 MHz
1/2 SYSCLKOUT
75 MHz
1/4 SYSCLKOUT
37.5 MHz
The relationship between SYSCLKOUT and XTIMCLK is shown in
XTIMING0
XTIMING1
XTIMING2
XTIMING6
XTIMING7
XBANK
LEAD/ACTIVE/TRAIL
C28x
CPU
SYSCLKOUT
/2
1
(A)
XTIMCLK
/2
1
(A)
0
1
0
XCLKOUT
0
0
XINTCNF2
(XTIMCLK)
XINTCNF2
(CLKMODE)
XINTCNF2
(CLKOFF)
(A)
Default value after reset
Figure 6-30. Relationship Between XTIMCLK and SYSCLKOUT
128
Electrical Specifications
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