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SPRS174S – APRIL 2001 – REVISED MARCH 2011
6.22 External Interface (XINTF) Timing
Each XINTF access consists of three parts: Lead, Active, and Trail. The user configures the
Lead/Active/Trail wait states in the XTIMING registers. There is one XTIMING register for each XINTF
zone.
shows the relationship between the parameters configured in the XTIMING register and
the duration of the pulse in terms of XTIMCLK cycles.
Table 6-30. Relationship Between Parameters Configured in XTIMING and Duration of Pulse
(1) (2)
DESCRIPTION
LR
AR
TR
LW
AW
TW
(1)
(2)
Lead period, read access
Active period, read access
Trail period, read access
Lead period, write access
Active period, write access
Trail period, write access
DURATION (ns)
X2TIMING = 0
XRDLEAD × t
c(XTIM)
(XRDACTIVE + WS + 1) × t
c(XTIM)
XRDTRAIL × t
c(XTIM)
XWRLEAD × t
c(XTIM)
(XWRACTIVE + WS + 1) × t
c(XTIM)
XWRTRAIL × t
c(XTIM)
X2TIMING = 1
(XRDLEAD × 2) × t
c(XTIM)
(XRDACTIVE × 2 + WS + 1) × t
c(XTIM)
(XRDTRAIL × 2) × t
c(XTIM)
(XWRLEAD × 2) × t
c(XTIM)
(XWRACTIVE × 2 + WS + 1) × t
c(XTIM)
(XWRTRAIL × 2) × t
c(XTIM)
t
c(XTIM)
– Cycle time, XTIMCLK
WS refers to the number of wait states inserted by hardware when using XREADY. If the zone is configured to ignore XREADY
(USEREADY = 0), then WS = 0.
Minimum wait state requirements must be met when configuring each zone’s XTIMING register. These
requirements are in addition to any timing requirements as specified by that device’s data sheet. No
internal device hardware is included to detect illegal settings.
●
If the XREADY signal is ignored (USEREADY = 0), then:
1.
Lead:
LR
≥
t
c(XTIM)
LW
≥
t
c(XTIM)
These requirements result in the following XTIMING register configuration restrictions (no hardware to
detect illegal XTIMING configurations):
XRDLEAD
≥
1
XRDACTIVE
≥
0
XRDTRAIL
≥
0
XWRLEAD
≥
1
XWRACTIVE
≥
0
XWRTRAIL
≥
0
X2TIMING
0, 1
Examples of valid and invalid timing when not sampling XREADY (no hardware to detect illegal XTIMING
configurations):
XRDLEAD
Invalid
Valid
0
1
XRDACTIVE
0
0
XRDTRAIL
0
0
XWRLEAD
0
1
XWRACTIVE
0
0
XWRTRAIL
0
0
X2TIMING
0, 1
0, 1
Copyright © 2001–2011, Texas Instruments Incorporated
Electrical Specifications
125
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