TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
SPRS174S–APRIL 2001–REVISED MARCH 2011
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If the XREADY signal is sampled in the synchronous mode (USEREADY = 1, READYMODE = 0),
then:
1.
Lead:
LR ≥ tc(XTIM)
LW ≥ tc(XTIM)
2.
Active:
AR ≥ 2 × tc(XTIM)
AW ≥ 2 × tc(XTIM)
NOTE: Restriction does not include external hardware wait states.
These requirements result in the following XTIMING register configuration restrictions (no hardware to
detect illegal XTIMING configurations):
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥ 1
≥ 1
≥ 0
≥ 1
≥ 1
≥ 0
0, 1
Examples of valid and invalid timing when using synchronous XREADY (no hardware to detect illegal
XTIMING configurations):
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
0, 1
Invalid
Invalid
Valid
0
1
1
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0, 1
0, 1
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Electrical Specifications
Copyright © 2001–2011, Texas Instruments Incorporated
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