TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
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SPRS174S–APRIL 2001–REVISED MARCH 2011
●
If the XREADY signal is sampled in the asynchronous mode (USEREADY = 1,
READYMODE = 1), then:
1.
Lead:
LR ≥ tc(XTIM)
LW ≥ tc(XTIM)
2.
Active:
AR ≥ 2 × tc(XTIM)
AW ≥ 2 × tc(XTIM)
NOTE: Restriction does not include external hardware wait states
3.
Lead + Active:
LR + AR ≥ 4 × tc(XTIM)
LW + AW ≥ 4 × tc(XTIM)
NOTE: Restriction does not include external hardware wait states
These requirements result in the following XTIMING register configuration restrictions (no hardware to
detect illegal XTIMING configurations):
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥ 1
≥ 2
0
≥ 1
≥ 2
0
0, 1
or (no hardware to detect illegal XTIMING configurations):
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥ 2
≥ 1
0
≥ 2
≥ 1
0
0, 1
Examples of valid and invalid timing when using asynchronous XREADY (no hardware to detect illegal
XTIMING configurations):
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
Invalid
Invalid
Invalid
Valid
0
1
1
1
1
2
0
0
1
1
2
1
0
0
0
0
0
0
0
1
1
1
1
2
0
0
1
1
2
1
0
0
0
0
0
0
0, 1
0, 1
0
1
Valid
0, 1
0, 1
Valid
Copyright © 2001–2011, Texas Instruments Incorporated
Electrical Specifications
127
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