SPRS174S – APRIL 2001 – REVISED MARCH 2011
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Table 6-45. AC Specifications
PARAMETER
SINAD
SNR
THD (100 kHz)
ENOB (SNR)
SFDR
Signal-to-noise ratio + distortion
Signal-to-noise ratio
Total harmonic distortion
Effective number of bits
Spurious free dynamic range
MIN
TYP
62
62
–68
10.1
69
MAX
UNIT
dB
dB
dB
Bits
dB
6.30.3 Current Consumption for Different ADC Configurations
Table 6-46. Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)
(1)
I
DDA
(TYP)
(2)
40 mA
I
DDAIO
(TYP)
1 µA
I
DD1
(TYP)
0.5 mA
ADC OPERATING MODE/CONDITIONS
Mode A (Operational Mode):
•
BG and REF enabled
•
PWD disabled
Mode B:
•
ADC clock enabled
•
BG and REF enabled
•
PWD enabled
Mode C:
•
ADC clock enabled
•
BG and REF disabled
•
PWD enabled
Mode D:
•
ADC clock disabled
•
BG and REF disabled
•
PWD enabled
7 mA
0
5 µA
1 µA
0
5 µA
1 µA
0
0
(1)
(2)
Test Conditions:
• SYSCLKOUT = 150 MHz
• ADC module clock = 25 MHz
• ADC performing a continuous conversion of all 16 channels in Mode A
I
DDA
– includes current into V
DDA1
/V
DDA2
and AVDDREFBG
R
s
ADCIN0
R
on
1 kW
Switch
Source
Signal
ac
C
p
10 pF
C
h
1.25 pF
28x DSP
Typical Values of the Input Circuit Components:
Switch Resistance (R
on
): 1 k
W
Sampling Capacitor (C
h
): 1.25 pF
Parasitic Capacitance (C
p
): 10 pF
Source Resistance (R
s
): 50
W
Figure 6-39. ADC Analog Input Impedance Model
144
Electrical Specifications
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