TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
www.ti.com.cn
表9-18. PIE MUXed Peripheral Interrupt Vector Table
INTx.8(1)
WAKEINT
(LPM/WD)
0xD4E
INTx.7
INTx.6
ADCINT9
(ADC)
INTx.5
INTx.4
INTx.3
INTx.2
ADCINT2
(ADC)
INTx.1
ADCINT1
(ADC)
INT1.y
INT2.y
INT3.y
INT4.y
INT5.y
INT6.y
INT7.y
INT8.y
INT9.y
INT10.y
INT11.y
INT12.y
TINT0
XINT2
XINT1
Reserved
(TIMER 0)
0xD4C
Ext. int. 2
0xD48
Ext. int. 1
0xD46
–
0xD4A
0xD44
0xD42
0xD40
Reserved
Reserved
Reserved
Reserved
EPWM4_TZINT
(ePWM4)
0xD56
EPWM3_TZINT
(ePWM3)
0xD54
EPWM2_TZINT
(ePWM2)
0xD52
EPWM1_TZINT
(ePWM1)
0xD50
–
–
–
–
0xD5E
0xD5C
0xD5A
0xD58
Reserved
Reserved
Reserved
Reserved
EPWM4_INT
(ePWM4)
0xD66
EPWM3_INT
(ePWM3)
0xD64
EPWM2_INT
(ePWM2)
0xD62
EPWM1_INT
(ePWM1)
0xD60
–
–
–
–
0xD6E
0xD6C
0xD6A
0xD68
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ECAP1_INT
(eCAP1)
0xD70
–
–
–
–
–
–
–
0xD7E
0xD7C
0xD7A
0xD78
0xD76
0xD74
0xD72
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
–
–
–
–
–
–
–
–
0xD8E
0xD8C
0xD8A
0xD88
0xD86
0xD84
0xD82
0xD80
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SPITXINTA
(SPI-A)
SPIRXINTA
(SPI-A)
–
–
–
–
–
–
0xD9E
0xD9C
0xD9A
0xD98
0xD96
0xD94
0xD92
0xD90
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
–
–
–
–
–
–
–
–
0xDAE
0xDAC
0xDAA
0xDA8
0xDA6
0xDA4
0xDA2
0xDA0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
I2CINT2A
(I2C-A)
I2CINT1A
(I2C-A)
–
–
–
–
–
–
0xDBE
0xDBC
0xDBA
0xDB8
0xDB6
0xDB4
0xDB2
0xDB0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SCITXINTA
(SCI-A)
SCIRXINTA
(SCI-A)
–
–
–
–
–
–
0xDCE
0xDCC
0xDCA
0xDC8
0xDC6
0xDC4
0xDC2
0xDC0
ADCINT8
(ADC)
ADCINT7
(ADC)
ADCINT6
(ADC)
ADCINT5
(ADC)
ADCINT4
(ADC)
ADCINT3
(ADC)
ADCINT2
(ADC)
ADCINT1
(ADC)
0xDDE
0xDDC
0xDDA
0xDD8
0xDD6
0xDD4
0xDD2
0xDD0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
–
–
–
–
–
–
–
–
0xDEE
0xDEC
0xDEA
0xDE8
0xDE6
0xDE4
0xDE2
0xDE0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
XINT3
Ext. Int. 3
0xDF0
–
–
–
–
–
–
–
0xDFE
0xDFC
0xDFA
0xDF8
0xDF6
0xDF4
0xDF2
(1) Out of 96 possible interrupts, some interrupts are not used. These interrupts are reserved for future devices. These interrupts can be
used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a
peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR.
To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
a. No peripheral within the group is asserting interrupts.
b. No peripheral interrupts are assigned to the group (for example, PIE groups 5, 7, or 11) .
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