TMS320DM6437
Digital Media Processor
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SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
6.24.2 JTAG Electrical Data/Timing
Table 6-116. Timing Requirements for JTAG Test Port (see Figure 6-59)
-400
-500
-600
NO.
UNIT
MIN
MAX
1
3
4
tc(TCK)
Cycle time, TCK
33
2.5
ns
ns
ns
tsu(TDIV-TCKH)
th(TCKH-TDIV)
Setup time, TDI/TMS/TRST valid before TCK high
Hold time, TDI/TMS/TRST valid after TCK high
16.5
Table 6-117. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port
(see Figure 6-59)
-400
-500
-600
NO.
PARAMETER
UNIT
MIN
MAX
2
td(TCKL-TDOV)
Delay time, TCK low to TDO valid
0
14
ns
1
TCK
TDO
2
2
4
3
TDI/TMS/TRST
Figure 6-59. JTAG Test-Port Timing
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