TMS320DM6437
Digital Media Processor
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SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
1
2
MRCLK (Input)
MRXD3−MRXD0,
MRXDV, MRXER (Inputs)
Figure 6-48. EMAC Receive Interface Timing
Table 6-88. Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit
10/100 Mbit/s(1) (see Figure 6-49)
-400
-500
-600
NO.
UNIT
MIN
MAX
1
td(MTCLKH-MTXD)
Delay time, MTCLK high to transmit selected signals valid
2
25
ns
(1) Transmit selected signals include: MTXD3-MTXD0, and MTXEN.
1
MTCLK (Input)
MTXD3−MTXD0,
MTXEN (Outputs)
Figure 6-49. EMAC Transmit Interface Timing
280
Peripheral Information and Electrical Specifications
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