TMS320DM6437
Digital Media Processor
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SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
6.17.2 EMAC Electrical Data/Timing
Table 6-85. Timing Requirements for MRCLK (see Figure 6-46)
-400
-500
-600
NO.
UNIT
10 Mbps
100 Mbps
MIN MAX MIN MAX
1
2
3
tc(MRCLK)
Cycle time, MRCLK
400
140
140
40
14
14
ns
ns
ns
tw(MRCLKH) Pulse duration, MRCLK high
tw(MRCLKL) Pulse duration, MRCLK low
1
2
3
MRCLK
Figure 6-46. MRCLK Timing (EMAC - Receive)
Table 6-86. Timing Requirements for MTCLK (see Figure 6-46)
-400
-500
-600
NO.
UNIT
10 Mbps
100 Mbps
MIN MAX MIN MAX
1
2
3
tc(MTCLK)
Cycle time, MTCLK
400
140
140
40
14
14
ns
ns
ns
tw(MTCLKH) Pulse duration, MTCLK high
tw(MTCLKL)
Pulse duration, MTCLK low
1
2
3
MTCLK
Figure 6-47. MTCLK Timing (EMAC - Transmit)
Table 6-87. Timing Requirements for EMAC MII Receive 10/100 Mbit/s(1) (see Figure 6-48)
-400
-500
-600
NO.
UNIT
MIN
8
MAX
1
2
tsu(MRXD-MRCLKH)
th(MRCLKH-MRXD)
Setup time, receive selected signals valid before MRCLK high
Hold time, receive selected signals valid after MRCLK high
ns
ns
8
(1) Receive selected signals include: MRXD3-MRXD0, MRXDV, and MRXER.
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Peripheral Information and Electrical Specifications
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