TMS320DM6437
Digital Media Processor
www.ti.com
SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
Table 6-81. Ethernet MAC (EMAC) Control Registers (continued)
HEX ADDRESS RANGE
01C8 0104
01C8 0108
01C8 010C
01C8 0110
01C8 0114
01C8 0120
01C8 0124
01C8 0128
01C8 012C
01C8 0130
01C8 0134
01C8 0138
01C8 013C
01C8 0140
01C8 0144
01C8 0148
01C8 014C
01C8 0150
01C8 0154
01C8 0158
01C8 015C
01C8 0160
01C8 0164
01C8 0168
01C8 016C
01C8 0170
01C8 0174
01C8 01D0
01C8 01D4
01C8 01D8
01C8 01DC
01C8 01E0
01C8 01E4
01C8 01E8
01C8 01EC
01C8 0200 - 01C8 02FC
01C8 0500
01C8 0504
01C8 0508
01C8 0600
01C8 0604
01C8 0608
01C8 060C
01C8 0610
01C8 0614
01C8 0618
01C8 061C
ACRONYM
RXUNICASTSET
RXUNICASTCLEAR
RXMAXLEN
REGISTER NAME
Receive Unicast Enable Set Register
Receive Unicast Clear Register
Receive Maximum Length Register
RXBUFFEROFFSET
RXFILTERLOWTHRESH
RX0FLOWTHRESH
RX1FLOWTHRESH
RX2FLOWTHRESH
RX3FLOWTHRESH
RX4FLOWTHRESH
RX5FLOWTHRESH
RX6FLOWTHRESH
RX7FLOWTHRESH
RX0FREEBUFFER
RX1FREEBUFFER
RX2FREEBUFFER
RX3FREEBUFFER
RX4FREEBUFFER
RX5FREEBUFFER
RX6FREEBUFFER
RX7FREEBUFFER
MACCONTROL
MACSTATUS
Receive Buffer Offset Register
Receive Filter Low Priority Frame Threshold Register
Receive Channel 0 Flow Control Threshold Register
Receive Channel 1 Flow Control Threshold Register
Receive Channel 2 Flow Control Threshold Register
Receive Channel 3 Flow Control Threshold Register
Receive Channel 4 Flow Control Threshold Register
Receive Channel 5 Flow Control Threshold Register
Receive Channel 6 Flow Control Threshold Register
Receive Channel 7 Flow Control Threshold Register
Receive Channel 0 Free Buffer Count Register
Receive Channel 1 Free Buffer Count Register
Receive Channel 2 Free Buffer Count Register
Receive Channel 3 Free Buffer Count Register
Receive Channel 4 Free Buffer Count Register
Receive Channel 5 Free Buffer Count Register
Receive Channel 6 Free Buffer Count Register
Receive Channel 7 Free Buffer Count Register
MAC Control Register
MAC Status Register
EMCONTROL
FIFOCONTROL
MACCONFIG
Emulation Control Register
FIFO Control Register (Transmit and Receive)
MAC Configuration Register
SOFTRESET
Soft Reset Register
MACSRCADDRLO
MACSRCADDRHI
MACHASH1
MAC Source Address Low Bytes Register (Lower 32-bits)
MAC Source Address High Bytes Register (Upper 16-bits)
MAC Hash Address Register 1
MACHASH2
MAC Hash Address Register 2
BOFFTEST
Back Off Test Register
TPACETEST
Transmit Pacing Algorithm Test Register
Receive Pause Timer Register
RXPAUSE
TXPAUSE
Transmit Pause Timer Register
(see Table 6-82)
MACADDRLO
MACADDRHI
EMAC Statistics Registers
MAC Address Low Bytes Register
MAC Address High Bytes Register
MACINDEX
MAC Index Register
TX0HDP
Transmit Channel 0 DMA Head Descriptor Pointer Register
Transmit Channel 1 DMA Head Descriptor Pointer Register
Transmit Channel 2 DMA Head Descriptor Pointer Register
Transmit Channel 3 DMA Head Descriptor Pointer Register
Transmit Channel 4 DMA Head Descriptor Pointer Register
Transmit Channel 5 DMA Head Descriptor Pointer Register
Transmit Channel 6 DMA Head Descriptor Pointer Register
Transmit Channel 7 DMA Head Descriptor Pointer Register
TX1HDP
TX2HDP
TX3HDP
TX4HDP
TX5HDP
TX6HDP
TX7HDP
Submit Documentation Feedback
Peripheral Information and Electrical Specifications
275
TI [ TEXAS INSTRUMENTS ]
