TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Updated I2C data rate configuration descriptions in I2C Master Mode Configuration table (Page 32)
Added PLLSELECT bit to PASSPLLCTL1 Register (Page 155)
Updated PASS PLL Block Diagram to reflect the mux selected by PASSPLLCTL1[13] (Page 154)
Added SPI device-specific support details (Page 209)
Corrected that only the sticky bits in PCIe MMRs will be retained after soft reset (Page 135)
Revision C
Added note stating that both SGMII ports can be used for boot (Page 31)
Updated the DDR3 MMR descriptions and deleted the unrelated PCIe MMR descriptions for soft reset. (Page 135)
Corrected physical 36-bit addresses of DDR3 EMIF configuration/data (Page 27)
Added TeraNet connection figures and added bridge numbers to the connection tables. (Page 99)
Restricted Output Divide of SECCTL register to max value of divide by 2 (Page 143)
Updated DEVSPEED register for both silicon rev1.0 and 2.0 (Page 96)
Removed RESETFULLz parameter from 4b timing description (Page 123)
Added supported data rates for HyperLink (Page 212)
Changed chip level interrupt controller name from INTC to CIC (Page 162)
Changed TPCC to EDMA3CC and TPTC to EDMA3TC (Page 156)
Added PLLRST bit to DDR3PLLCTL1 register (Page 152)
Added PLLRST bit to PASSPLLCTL1 register (Page 155)
Deleted INTC0 register map address offset 0x4 and 0x8, which are Reserved (Page 181)
Corrected the SGMII SerDes clock to PASS clock in PASS PLL configuration description (Page 41)
Corrected PASS PLL clock from SRIOSGMIICLK to PASSCLK in the boot device values table for Ethernet. (Page 29)
Corrected the SPI and DDR3/HyperLink Config end addressed (Page 27)
Added the DDR3 PLL Initialization Sequence (Page 153)
Added the Main PLL and PLL Controller Initialization Sequence (Page 149)
Added the PASS PLL Initialization Sequence (Page 155)
Added HyperLink interrupt event section (Page 212)
Added events #144-159 to INTC2 event input table (Page 176)
Added DEVSPEED Register section. (Page 96)
Added more description to Boot Sequence section (Page 27)
Corrected a typo, changed DDRCLKN to DDRCLKP (Page 153)
Revision B
Removed section 7.1 Parameter Information (Page 120)
Corrected PASS PLL clock source description from Main PLL mux to CORECLK clock reference sources (Page 154)
Corrected MACID2 address from 0x02600114 to 0x02620114 (Page 223)
Added EMIF16 Electrical Data/Timing section (Page 220)
Added TSIP Electrical Data/Timing section (Page 218)
Updated SPI Timing section (Page 209)
Changed Data Rate 3 to Reserved from 12.5GBs in HyperLink configuration field table (Page 34)
Corrected the Device ID field to be bits 5 to 3 in Ethernet Configuration Field figure and table (Page 31)
Corrected the field bits of No Boot/EMIF16 configuration field figure and table (Page 30)
Revision A
Added note to RSISO register that both SRIOISO and SRISO will be set by boot ROM code during boot (Page 147)
Modified PCIe peripherals introduction in Features section (Page 13)
Removed AIF2ISO from Reset Isolation Register (Page 147)
Added information of on-chip divider (=3) for PA in the PLL Boot Configuration Settings section (Page 41)
Changed "no support for MSI" to "support for legacy INTx" for PCIe in legacy EP mode description in Device Status Register Field Descrip-
tions table (Page 79)
Changed "no support for MSI" to "support for legacy INTx" for PCIe legacy end point description in Device Configuration Pins table
(Page 74)
Added "The packet accelerator is coupled with network coprocessor" in the Packet Accelerator section (Page 222)
Added Network Coprocessor document link (Page 73)
234
Revision History
Copyright 2013 Texas Instruments Incorporated
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