TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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A Revision History
Revision D
Corrected NMI7-0 from bit fields 23-16 to bit fields 15-8 in LRSTNMIPINSTAT and LRSTNMIPINSTAT_CLR registers (Page 81)
Added Extended Boot Mode table in Boot Device Field section (Page 29)
Updated event "PO_VP_SMPSACK_INTR" to be Reserved in CIC3 event table (Page 181)
Updated Trace Electrical Timing tables and Timing diagrams (Page 230)
Updated event "PO_VCON_SMPSERR_INTR" be Reserved in CIC0/1 Event Inputs table (Page 170)
Added Boot Parameter Table section (Page 34)
Added new section "DDR3 Memory Controller Race Condition Consideration" to include the last 3 paragraphs originally in section 7.11.1
(Page 203)
Added REFCLK description in power sequencing section (Page 121)
Added table of Bootloader section in L2 SRAM in Boot Sequence section (Page 27)
Updated SYSCLK1 to REFCLK in power sequencing section to refer to the clock source of main PLL (Page 122)
Updated note in power sequencing that each supply must ramp monotonically and must reach a stable valid level within 20 ms.
(Page 122)
Corrected differential clock rise and fall time in the PLL timing table for the clock inputs that feed into the LJCB clock buffers (Page 150)
Changed all footnote references from CORECLK to SYSCLK1 (Page 228)
Updated PCIe privilege level from "Supervisor" to "Driven by PCIe module" (Page 191)
Corrected "Reserved" to be "Assert local reset to all CorePacs" in LRESET and NMI Decoding table (Page 187)
Added MPU Registers Reset Values section (Page 201)
Added "Initial Startup" row for CVDD in Recommended Operating Conditions table (Page 117)
Added DDR3PLLCTL1 and PASSPLLCTL1 registers to Device Status Control Registers table (Page 77)
Updated all SerDes clocks to discrete frequencies in the Clock Input Timing Requirements table (Page 149)
Corrected tj(CORECLKN/P) max value from 100 to 0.02*tc(CORECLKN/P) (Page 150)
Corrected tj(DDRCLKN/P) max value from 0.025*tc(DDRCLKN/P) to 0.02*tc(DDRCLKN/P) (Page 153)
Corrected tj(PASSCLKN/P) max value from 100 to 0.02*tc(PASSCLKN/P) (Page 156)
Updated the descriptions of how Semaphore module is accessible (Page 229)
Added Debug Subsystem Configuration region to memory map table (Page 23)
Added HOUT timing diagram in Host Interrupt Output section (Page 188)
Added note to DDR3 PLL initialization sequence (Page 153)
Corrected MPU0 Memory Protection End Address from 0x026203FF to 0x026207FF (Page 190)
Revised IPCGRH register description (Page 89)
Corrected DDR3 transfer rate from 1033 MTS to 1066 MTS (Page 203)
Added CVDD and SmartReflex voltage parameter in SmartReflex switching table (Page 127)
Removed DDR3 PLL initialization sequence from data manual to PLL controller user guide (Page 153)
Removed PASS PLL initialization sequence from data manual to PLL controller user guide (Page 155)
Updated chip select from CS[5:2] to CE[3:0] in EMIF16 Peripheral section (Page 220)
Updated EMIF chip select from CS[5:2] to CE[3:0] in Memory Map Summary table (Page 27)
Updated DDR3 PLL initialization sequence (Page 153)
Added footnote for DDR3 EMIF data in memory map summary table (Page 27)
Updated Tracer descriptions across the data manual (Page 21)
Corrected PASSCLK(N/P) max cycle time from 6.4 ns to 25 ns (Page 156)
Updated the Timer numbering across the whole document (Page 22)
Corrected PASS PLL clock to SRIOSGMIICLK in the boot device values table for Ethernet. (Page 29)
Added clarification for RESETSTATz input current (Page 118)
Added note for VCNTLID register that it is available for debug purpose only (Page 130)
Added STM Trace Switching Characteristics table (Page 230)
Removed the incorrect description of 16-Bit EMIF in Features section (Page 13)
Updated th(MDCLKH-MDIO) value from 10 ns to 0 ns in MDIO Timing Requirements table (Page 225)
Updated the description of NAND in the footnote of memory map summary table (Page 27)
Updated tw(DPnH) and tw(DPnL) descriptions in Trace Switching Characteristics tables (Page 230)
Updated I2C master mode table that bits[9:8] are used for mode selection (Page 32)
Updated the I2C passive mode table that bits[9:8] are used for mode selection and actual value on the bus is 0x19+bits[7:5] (Page 33)
Copyright 2013 Texas Instruments Incorporated
Revision History 233
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