TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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Table 7-77
(see Figure 7-49)
Timing Requirements for TSIP 1x Mode (1)
No.
Min
122.1 (2)
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
12
13
14
15
16
17
18
19
20
tc(CLK)
Cycle time, CLK rising edge to next CLK rising edge
tw(CLKL)
Pulse duration, CLK low
0.4×tc(CLK)
0.4×tc(CLK)
tw(CLKH)
Pulse duration, CLK high
tt(CLK)
Transition time, CLK high to low or CLK low to high
Setup time, FS valid before rising CLK
Hold time, FS valid after rising CLK
Setup time, TR valid before rising CLK
Hold time, TR valid after rising CLK
Delay time, CLK low to TX valid
Disable time, CLK low to TX Hi-Z
2
tsu(FS-CLK)
th(CLK-FS)
tsu(TR-CLK)
th(CLK-TR)
td(CLKL-TX)
tdis(CLKH-TXZ)
5
5
5
5
1
2
12
10
End of Table 7-77
1 Polarities of XMTFSYNCP = 0b, XMTFCLKP = 0, XMTDCLKP = 0b, RCVFSYNCP = 0, RCVFCLKP = 0, RCVDCLKP = 1. If the polarity of any of the signals is inverted, then the timing
references of that signal are also inverted.
2 Timing shown is for 8.192 Mbps links. Timing for 16.384 Mbps and 32.768 Mbps links is 61 ns and 30.5 ns, respectively.
Figure 7-49
CLKA/B
TSIP 1x Timing Diagram(1)
11
12 13
16
15
FSA/B
17
18
TR[n]
TX[n]
ts127-3
ts127-2
ts127-2
ts127-1
ts127-1
ts127-0
ts127-0
ts000-7
ts000-6
ts000-5
ts000-5
ts000-4
ts000-4
ts000-3
ts000-3
ts000-2
ts000-2
ts000-1
ts000-1
ts000-0
ts000-0
19
ts127-3
ts000-7
ts000-6
1 Example timeslot numbering shown is for 8.192 Mbps links; 16.384 Mbps links have timeslots numbered 0 through 255 and 32.768 Mbps links have timeslots numbered 0
through 511. The data timing shown relative to the clock and frame sync signals would require a RCVDATD=1023 and a XMTDATD=1023.
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