TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
7.10.2.4 MPU Registers Reset Values
Table 7-62
Programmable Range n Registers Reset Values for MPU0
MPU0 (Main CFG TeraNet)
Programmable Start Address
Range
End Address
Memory Page Protection
Attribute (PROGn_MPPA)
(PROGn_MPSAR)
0x01D0_0000
0x01F0_0000
0x0200_0000
0x01E0_0000
0x021C_0000
0x021F_0000
0x0220_0000
0x0231_0000
0x0232_0000
0x0233_0000
0x0235_0000
0x0240_0000
0x0250_0000
0x0253_0000
0x0260_0000
0x0262_0000
(PROGn_MPEAR)
0x01D8_03FF
0x01F7_FFFF
0x0209_FFFF
0x01EB_FFFF
0x021E_0FFF
0x021F_7FFF
0x022F_03FF
0x0231_03FF
0x0232_03FF
0x0233_03FF
0x0235_0FFF
0x024B_3FFF
0x0252_03FF
0x0254_03FF
0x0260_FFFF
0x0262_07FF
Memory Protection
PROG0
0x03FF_FCB6
0x03FF_FC80
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FC80
0x03FF_FC80
0x03FF_FCB6
0x03FF_FCB4
0x03FF_FCB4
0x03FF_FCB4
0x03FF_FCB4
0x03FF_FCB6
0x03FF_FCB4
0x03FF_FCB6
0x03FF_FCB4
0x03FF_FCB4
Tracers
PROG1
Reserved
PROG2
NETCP
PROG3
TSIP
PROG4
Reserved
PROG5
Reserved
PROG6
Timers
PROG7
PLL
PROG8
GPIO
PROG9
SmartReflex
PROG10
PROG11
PROG12
PROG13
PROG14
PROG15
End of Table 7-62
PSC
DEBUG_SS, Tracer Formatters
Reserved
I2C, UART
CICs
Chip-level Registers
Table 7-63
Programmable Range n Registers Reset Values for MPU1
MPU1 (QM_SS DATA PORT)
Programmable Start Address
End Address
(PROGn_MPEAR)
Memory Page Protection
Attribute (PROGn_MPPA)
Range
(PROGn_MPSAR)
0x3400_0000
0x3402_0000
0x3406_0000
0x3406_8000
0x340B_8000
Memory Protection
PROG0
0x3401_FFFF
0x3405_FFFF
0x3406_7FFF
0x340B_7FFF
0x340B_FFFF
0x03FF_FC80
0x000F_FCB6
0x03FF_FCB4
0x03FF_FC80
0x03FF_FCB6
Queue Manager subsystem
data
PROG1
PROG2
PROG3
PROG4
End of Table 7-63
Copyright 2013 Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 201
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