TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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7.10.2 MPU Programmable Range Registers
7.10.2.1 Programmable Range n Start Address Register (PROGn_MPSAR)
The programmable address start register holds the start address for the range. This register is writeable by a
supervisor entity only. If NS = 0 (non-secure mode) in the associated MPPA register, then the register is also
writeable only by a secure entity.
The start address must be aligned on a page boundary. The size of the page is 1K byte. The size of the page determines
the width of the address field in MPSAR and MPEAR.
Figure 7-33
Programmable Range n Start Address Register (PROGn_MPSAR)
31
10
9
0
START_ADDR
R/W
Reserved
R
Legend: R = Read only; R/W = Read/Write
Table 7-59
Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions
Bit
Field
Description
31 – 10
9 – 0
START_ADDR
Reserved
Start address for range n.
Reserved and these bits always read as 0.
End of Table 7-59
7.10.2.2 Programmable Range n End Address Register (PROGn_MPEAR)
The programmable address end register holds the end address for the range. This register is writeable by a supervisor
entity only. If NS = 0 (non-secure mode) in the associated MPPA register then the register is also only writeable by
a secure entity.
The end address must be aligned on a page boundary. The size of the page depends on the MPU number. The page
size for MPU1 is 1K byte and for MPU2 it is 64K bytes. The size of the page determines the width of the address field
in MPSAR and MPEAR
Figure 7-34
Programmable Range n End Address Register (PROGn_MPEAR)
31
10
9
0
END_ADDR
R/W
Reserved
R
Legend: R = Read only; R/W = Read/Write
Table 7-60
Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions
Bit
Field
Description
31 – 10
9 – 0
END_ADDR
Reserved
End address for range n.
Reserved and these bits always read as 3FFh.
End of Table 7-60
198
Peripheral Information and Electrical Specifications
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