TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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Table 7-61
Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Field Descriptions
(Part 2 of 2)
Bit
Field
Description
15
AID5
AID4
AID3
AID2
AID1
AID0
AIDX
Controls permission check of ID = 5
0 = AID is not checked for permissions
1 = AID is checked for permissions
14
13
12
11
10
9
Controls permission check of ID = 4
0 = AID is not checked for permissions
1 = AID is checked for permissions
Controls permission check of ID = 3
0 = AID is not checked for permissions
1 = AID is checked for permissions
Controls permission check of ID = 2
0 = AID is not checked for permissions
1 = AID is checked for permissions
Controls permission check of ID = 1
0 = AID is not checked for permissions
1 = AID is checked for permissions
Controls permission check of ID = 0
0 = AID is not checked for permissions
1 = AID is checked for permissions
Controls permission check of ID > 15
0 = AID is not checked for permissions
1 = AID is checked for permissions
8
7
Reserved
NS
Always reads as 0.
Non-secure access permission
0 = Only secure access allowed.
1 = Non-secure access allowed.
6
5
4
3
2
1
0
EMU
SR
Emulation (debug) access permission. This bit is ignored if NS = 1
0 = Debug access not allowed.
1 = Debug access allowed.
Supervisor Read permission
0 = Access not allowed.
1 = Access allowed.
SW
SX
Supervisor Write permission
0 = Access not allowed.
1 = Access allowed.
Supervisor Execute permission
0 = Access not allowed.
1 = Access allowed.
UR
User Read permission
0 = Access not allowed.
1 = Access allowed
UW
UX
User Write permission
0 = Access not allowed.
1 = Access allowed.
User Execute permission
0 = Access not allowed.
1 = Access allowed.
End of Table 7-611
200
Peripheral Information and Electrical Specifications
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