TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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6.4 Power Supply to Peripheral I/O Mapping
(1) (2)
Table 6-4
Power Supply to Peripheral I/O Mapping
Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
Power Supply I/O Buffer Type
Associated Peripheral
CORECLK(P|N) PLL input buffer
SRIOSGMIICLK(P|N) SerDes PLL input buffer
DDRCLK(P|N) PLL input buffer
CVDD
Supply Core Voltage
LJCB
PCIECLK(P|N) SERDES PLL input buffer
MCMCLK(P|N) SERDES PLL input buffer
PASSCLK(P|N) PLL input buffer
DVDD15 1.5-V supply I/O voltage
DDR3 (1.5 V)
All DDR3 memory controller peripheral I/O buffer
All GPIO peripheral I/O buffer
All JTAG and EMU peripheral I/O buffer
All Timer peripheral I/O buffer
All SPI peripheral I/O buffer
All RESETs, NMI, Control peripheral I/O buffer
All SmartReflex peripheral I/O buffer
All Hyperlink sideband peripheral I/O buffer
All MDIO peripheral I/O buffer
LVCMOS (1.8 V)
DVDD18 1.8-V supply I/O voltage
All UART peripheral I/O buffer
All TSIP0 and TSIP1 peripheral I/O buffer
All EMIF16 peripheral I/O buffer
Open-drain (1.8V) All I2C peripheral I/O buffer
VDDT1
VDDT2
Hyperlink SerDes termination and analogue front-end supply
SerDes/CML
Hyperlink SerDes CML IO buffer
SRIO/SGMII/PCIE SerDes termination and analogue front-end
supply
SerDes/CML
SRIO/SGMII/PCIE SerDes CML IO buffer
End of Table 6-4
1 Please note that this table does not attempt to describe all functions of all power supply terminals but only those whose purpose it is to power peripheral I/O buffers and
clock input buffers.
2 Please see the Hardware Design Guide for KeyStone Devices in ‘‘Related Documentation from Texas Instruments’’ on page 73 for more information about individual
peripheral I/O.
Copyright 2013 Texas Instruments Incorporated
Device Operating Conditions
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