TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
www.ti.com
Figure 7-51
EMIF16 EM_WAIT Read Timing Diagram
Setup Strobe
Extended Due to EM_WAIT
Strobe
Hold
EM_CS[5:2]
EM_BA[1:0]
EM_A[21:0]
EM_D[15:0]
EM_OE
14
11
2
2
EM_WAIT
Deasserted
Asserted
Figure 7-52
EMIF16 EM_WAIT Write Timing Diagram
Setup Strobe
Extended Due to EM_WAIT
Strobe
Hold
EM_CS[5:2]
EM_BA[1:0]
EM_A[21:0]
EM_D[15:0]
EM_WE
28
25
2
2
EM_WAIT
Deasserted
Asserted
7.19 Packet Accelerator
The packet accelerator provides L2 to L4 classification functionalities. It supports classification for Ethernet, VLAN,
MPLS over Ethernet, IPv4/6, GRE over IP, and other session identification over IP such as TCP and UDP ports. It
maintains 8K multiple-in, multiple-out hardware queues. It also provides checksum capability as well as some QoS
capabilities. It enables a single IP address to be used for a multi-core device. It can process up to 1.5 M pps. The
packet accelerator is coupled with the network coprocessor. For more information, see the Packet Accelerator (PA)
for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 69.
7.20 Security Accelerator
The security accelerator provides wire-speed processing on 1-Gbps Ethernet traffic on IPSec, SRTP, and 3GPP Air
interface security protocols. It functions on the packet level with the packet and the associated security context being
one of these above three types. The security accelerator is coupled with network coprocessor, and receives the packet
descriptor containing the security context in the buffer descriptor, and the data to be encrypted/decrypted in the
linked buffer descriptor. For more information, see the Security Accelerator (SA) for KeyStone Devices User Guide in
‘‘Related Documentation from Texas Instruments’’ on page 69.
210
Peripheral Information and Electrical Specifications
Copyright 2012 Texas Instruments Incorporated
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