TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
www.ti.com
There is one Time Synchronization (CPTS) submodule in the Ethernet switch module for Time Synchronization.
Programming this register selects the clock source for the CPTS_RCLK. Please see the Gigabit Ethernet (GbE) Switch
Subsystem for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 69 for the
register address and other details about the Time Synchronization module. The register CPTS_RFTCLK_SEL for
reference clock selection of Time Synchronization submodule is shown in Figure 7-55.
Figure 7-55
CPTS_RFTCLK_SEL Register
31
3
2
0
Reserved
R - 0
CPTS_RFTCLK_SEL
RW - 0
Legend: R = Read only; -x, value is indeterminate
Table 7-78
CPTS_RFTCLK_SEL Register Field Descriptions
Description
Bit
Field
Reserved
31-3
2-0
Reserved. Read as zero.
CPTS_RFTCLK_SEL Reference Clock Select. This signal is used to control an external multiplexer that selects one of 8 clocks for time sync
reference (RFTCLK). This CPTS_RFTCLK_SEL value can be written only when the CPTS_EN bit is cleared to 0 in the
TS_CTL register.
000 = SYSCLK2
001 = SYSCLK3
010 = TIMI0
011 = TIMI1
100 = TSIP0 CLK_A
101 = TSIP0 CLK_B
110 = TSIP1 CLK_A
111 = TSIP1 CLK_B
End of Table 7-78
212
Peripheral Information and Electrical Specifications
Copyright 2012 Texas Instruments Incorporated
TI [ TEXAS INSTRUMENTS ]
