TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
www.ti.com
2 Device Overview
2.1 Device Characteristics
Table 2-1 shows the significant features of the device.
Table 2-1
Device Characteristics
HARDWARE FEATURES
TMS320C6672
DDR3 Memory Controller (64-bit bus width) [1.5 V I/O]
(clock source = DDRREFCLKN|P)
1
EDMA3 (16 independent channels) [DSP/2 clock rate]
1
2
1
1
2
1
1
1
2
1
1
1
EDMA3 (64 independent channels) [DSP/3 clock rate]
High-speed 1×/2x/4× Serial RapidIO Port (4 lanes)
PCIe (2 lanes)
10/100/1000 Ethernet
Management Data Input/Output (MDIO)
HyperLink
Peripherals
EMIF16
TSIP
SPI
UART
I2C
64-Bit Timers (configurable) (internal clock source = CPU/6 clock frequency)
Ten 64-bit (each configurable as two32-bit
timers)
General-Purpose Input/Output Port (GPIO)
Packet Accelerator
16
1
Accelerators
(1)
Security Accelerator
1
Size (Bytes)
5376KB
64KB L1 Program Memory [SRAM/Cache]
64KB L1 Data Memory [SRAM/Cache]
1024KB L2 Unified Memory/Cache
4096KB MSM SRAM
On-Chip Memory
Organization
128KB L3 ROM
C66x CorePac
Revision ID
See Section 5.5 ‘‘C66x CorePac Revision’’ on
page 108.
CorePac Revision ID Register (address location: 0181 2000h)
JTAGID register (address location: 0262 0018h)
See Section 3.3.3 ‘‘JTAG ID (JTAGID) Register
Description’’ on page 76
JTAG BSDL_ID
1500 (1.5 GHz)
Frequency
MHz
ns
1250 (1.25 GHz)
1000 (1.0 GHz)
0.67 ns (1.5 GHz)
0.8 ns (1.25 GHz)
1 ns (1.0 GHz)
Cycle Time
Voltage
Core (V)
SmartReflex variable supply
1.0 V, 1.5 V, and 1.8 V
0.040 μm
I/O (V)
Process Technology
BGA Package
Product Status (2)
μm
24 mm × 24 mm
841-Pin Flip-Chip Plastic BGA (CYP)
AI
Product Preview (PP), Advance Information (AI), or Production Data (PD)
End of Table 2-1
Copyright 2012 Texas Instruments Incorporated
Device Overview 17
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