欢迎访问ic37.com |
会员登录 免费注册
发布采购

TMS320C6672ACYP25 参数 Datasheet PDF下载

TMS320C6672ACYP25图片预览
型号: TMS320C6672ACYP25
PDF下载: 下载PDF文件 查看货源
内容描述: 多核固定和浮点数字信号处理器 [Multicore Fixed and Floating-Point Digital Signal Processor]
分类和应用: 数字信号处理器
文件页数/大小: 228 页 / 2410 K
品牌: TI [ TEXAS INSTRUMENTS ]
 浏览型号TMS320C6672ACYP25的Datasheet PDF文件第9页浏览型号TMS320C6672ACYP25的Datasheet PDF文件第10页浏览型号TMS320C6672ACYP25的Datasheet PDF文件第11页浏览型号TMS320C6672ACYP25的Datasheet PDF文件第12页浏览型号TMS320C6672ACYP25的Datasheet PDF文件第14页浏览型号TMS320C6672ACYP25的Datasheet PDF文件第15页浏览型号TMS320C6672ACYP25的Datasheet PDF文件第16页浏览型号TMS320C6672ACYP25的Datasheet PDF文件第17页  
TMS320C6672  
Multicore Fixed and Floating-Point Digital Signal Processor  
SPRS708C—February 2012  
www.ti.com  
1 Features  
• Two TMS320C66x™ DSP Core Subsystems (C66x  
CorePacs), Each with  
• Peripherals  
– Four Lanes of SRIO 2.1  
– 1.0 GHz, 1.25 GHz, or 1.5 GHz C66x  
› 1.24/2.5/3.125/5 GBaud Operation Supported  
Fixed/Floating-Point CPU Core  
Per Lane  
› 48 GMAC/Core for Fixed Point @ 1.5 GHz  
› 24 GFLOP/Core for Floating Point @ 1.5 GHz  
– Memory  
› Supports Direct I/O, Message Passing  
› Supports Four 1×, Two 2×, One 4×, and Two 1× +  
One 2× Link Configurations  
› 32K Byte L1P Per Core  
– PCIe Gen2  
› 32K Byte L1D Per Core  
› 512K Byte Local L2 Per Core  
› Single port supporting 1 or 2 lanes  
› Supports Up To 5 GBaud Per Lane  
– HyperLink  
• Multicore Shared Memory Controller (MSMC)  
› Supports Connections to Other KeyStone  
Architecture Devices Providing Resource  
Scalability  
– 4096KB MSM SRAM Memory Shared by Two DSP  
C66x CorePacs  
– Memory Protection Unit for Both MSM SRAM and  
DDR3_EMIF  
› Supports up to 50 Gbaud  
– Gigabit Ethernet (GbE) Switch Subsystem  
› Two SGMII Ports  
› Supports 10/100/1000 Mbps operation  
– 64-Bit DDR3 Interface (DDR3-1600)  
› 8G Byte Addressable Memory Space  
– 16-Bit EMIF  
• Multicore Navigator  
– 8192 Multipurpose Hardware Queues with Queue  
Manager  
– Packet-Based DMA for Zero-Overhead Transfers  
• Network Coprocessor  
› Support For Up To 256MB NAND Flash and  
– Packet Accelerator Enables Support for  
› Transport Plane IPsec, GTP-U, SCTP, PDCP  
› L2 User Plane PDCP (RoHC, Air Ciphering)  
16MB NOR Flash  
› Support For Asynchronous SRAM up to 1MB  
– Two Telecom Serial Ports (TSIP)  
› 1 Gbps Wire-Speed Throughput at 1.5 MPackets  
› Supports 1024 DS0s Per TSIP  
Per Second  
› Supports 2/4/8 Lanes at 32.768/16.384/8.192  
– Security Accelerator Engine Enables Support for  
Mbps Per Lane  
› IPSec, SRTP, 3GPP, WiMAX Air Interface, and  
– UART Interface  
– I2C Interface  
– 16 GPIO Pins  
SSL/TLS Security  
› ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC,  
CMAC, GMAC, AES, DES, 3DES, Kasumi, SNOW  
3G, SHA-1, SHA-2 (256-bit Hash), MD5  
– SPI Interface  
› Up to 2.8 Gbps Encryption Speed  
– Semaphore Module  
– Ten 64-Bit Timers  
– Three On-Chip PLLs  
• Commercial Temperature:  
– 0°C to 85°C  
• Extended Temperature:  
– - 40°C to 100°C  
Copyright 2012 Texas Instruments Incorporated  
ADVANCE INFORMATION concerns new products in the sampling or  
preproduction phase of development. Characteristic data and other specifications  
are subject to change without notice.  
 
 
 
 
 
 
 复制成功!