TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
www.ti.com
Figure 2-1 shows the DSP core functional units and data paths.
Figure 2-1
DSP Core Data Paths
Note:
src1
Default bus width
is 64 bits
(i.e. a register pair)
.L1
.S1
Register
File A
(A0, A1, A2,
...A31)
src2
dst
ST1
src1
src2
dst
src1
Data Path A
src1_hi
src2
.M1
src2_hi
dst2
dst1
LD1
DA1
32
src1
dst
32
32
.D1
32
src2
32
2
´
´
1
Register
File B
(B0, B1, B2,
...B31)
32
src2
32
32
DA2
LD2
.D2
32
dst
32
src1
32
dst1
dst2
src2_hi
.M2
src2
src1_hi
src1
Data Path B
dst
src2
.S2
src1
ST2
dst
src2
.L2
src1
32
32
Control
Register
20
Device Overview
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