ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇꢀ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢀ ꢐꢍ ꢕꢍ ꢀꢖꢗ ꢂꢍ ꢕ ꢔꢖꢗ ꢒꢘ ꢓ ꢆꢏ ꢂ ꢂꢓ ꢘ ꢂ
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005
INPUT AND OUTPUT CLOCKS (CONTINUED)
†‡§¶
timing requirements for ECLKIN for EMIFA and EMIFB
(see Figure 19)
−600
−720
−850
−1G
NO.
UNIT
MIN
MAX
16P
16P
#
6
CV
CV
= 1.2 V
= 1.1 V
ns
ns
ns
ns
ns
DD
1
t
Cycle time, ECLKIN
c(EKI)
#
7.5
DD
2
3
4
5
t
t
t
t
Pulse duration, ECLKIN high
Pulse duration, ECLKIN low
Transition time, ECLKIN
Period jitter, ECLKIN
2.7
2.7
w(EKIH)
w(EKIL)
t(EKI)
2
0.02E
ns
J(EKI)
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.
The reference points for the rise and fall transitions are measured at V MAX and V MIN.
IL IH
These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are
prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted.
E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB.
¶
#
Minimum ECLKIN cycle times must be met, even when ECLKIN is generated by an internal clock source. Minimum ECLKIN times are based
on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements. On the devices, 133-MHz
operation is achievable if the requirements of the EMIF Device Speed section are met.
1
5
4
2
ECLKIN
3
4
Figure 19. ECLKIN Timing for EMIFA and EMIFB
switching characteristics over recommended operating conditions for ECLKOUT1 for EMIFA and
§¶||ꢁ
EMIFB modules
(see Figure 20)
−600
−720
−850
−1G
NO.
PARAMETER
UNIT
MIN
MAX
ꢂ
1
2
3
4
5
6
t
t
t
t
t
t
Period jitter, ECLKOUT1
0
175
ps
ns
ns
ns
ns
ns
J(EKO1)
Pulse duration, ECLKOUT1 high
Pulse duration, ECLKOUT1 low
Transition time, ECLKOUT1
EH − 0.7 EH + 0.7
EL − 0.7 EL + 0.7
1
w(EKO1H)
w(EKO1L)
t(EKO1)
Delay time, ECLKIN high to ECLKOUT1 high
Delay time, ECLKIN low to ECLKOUT1 low
0.8
0.8
8
8
d(EKIH-EKO1H)
d(EKIL-EKO1L)
§
These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are
prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted.
E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB.
¶
||
The reference points for the rise and fall transitions are measured at V
MAX and V MIN.
OL
OH
ꢁ EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA or EMIFB.
ꢂ This cycle-to-cycle jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock.
83
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